公开(公告)号：US07525196B2

公开(公告)日：2009-04-28

申请号：US11336169

申请日：2006-01-19

申请人： Valery M. Dubin ,  Peter K. Moon

发明人： Valery M. Dubin ,  Peter K. Moon

IPC分类号： H01L23/48

CPC分类号： H01L21/76843 ,  H01L21/2885 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention includes a method of providing a substrate; sequentially forming a seed layer over the substrate and forming a protection layer over the seed layer; and sequentially removing the protection layer and forming a conductor over the seed layer.The present invention further includes a structure having a substrate, the substrate having a device; an insulator disposed over the substrate, the insulator having an opening, the opening disposed over the device; a barrier layer disposed over the opening; a seed layer disposed over the barrier layer; and a protection layer disposed over the seed layer.

摘要翻译： 本发明包括提供基板的方法; 在衬底上顺序地形成种子层，并在种子层上形成保护层; 并顺序地去除保护层并在种子层上形成导体。 本发明还包括具有基板的结构，所述基板具有装置; 设置在所述基板上的绝缘体，所述绝缘体具有开口，所述开口设置在所述装置上方; 设置在所述开口上方的阻挡层; 设置在阻挡层上的种子层; 以及设置在种子层上的保护层。

公开(公告)号：US20090090631A1

公开(公告)日：2009-04-09

申请号：US11906882

申请日：2007-10-03

申请人： Valery M. Dubin ,  James D. Blanchard

发明人： Valery M. Dubin ,  James D. Blanchard

IPC分类号： C25D3/02 ,  B21D39/00 ,  C25D17/00 ,  C25D17/06 ,  C25D17/10

CPC分类号： C25D17/06 ,  C25D17/004 ,  C25D21/12 ,  Y10T29/49908

摘要： In one embodiment, a substrate holder comprises a base supporting a substrate that includes a surface having a peripheral region. A cover may be assembled with the base and includes at least one opening exposing only a portion of the surface therethrough. A seal assembly substantially seals a region between the cover and base and further adjacent to the peripheral region of the substrate. An electrode includes at least one contact portion positioned within the region and extending over at least a portion of the peripheral region of the substrate. A compliant member comprises a polymeric material and may be positioned within the region between the at least one contact portion and either the peripheral region of the substrate or the cover. In other embodiments, an electroplating system is disclosed that may employ such a substrate holder.

摘要翻译： 在一个实施例中，衬底保持器包括支撑衬底的基底，该基底包括具有周边区域的表面。 盖可以与基座组装，并且包括至少一个仅暴露表面的一部分的开口。 密封组件基本上密封盖和基底之间的区域，并进一步邻近基底的周边区域。 电极包括位于该区域内的至少一个接触部分，并延伸至基底的周边区域的至少一部分。 顺应性构件包括聚合物材料并且可以位于至少一个接触部分和基底的周边区域或覆盖物之间的区域内。 在其他实施例中，公开了一种电镀系统，其可以采用这种衬底保持器。

公开(公告)号：US20090000957A1

公开(公告)日：2009-01-01

申请号：US11771536

申请日：2007-06-29

申请人： Valery M. Dubin ,  Nikolay Suetin

发明人： Valery M. Dubin ,  Nikolay Suetin

IPC分类号： C12Q1/00 ,  B01J19/00 ,  B23P17/04 ,  H01R43/00 ,  G01N27/26 ,  C12N11/00

CPC分类号： B01L3/502715 ,  B01J19/0046 ,  B01J2219/0061 ,  B01J2219/00612 ,  B01J2219/00626 ,  B01J2219/00628 ,  B01J2219/00644 ,  B01J2219/00653 ,  B01J2219/00659 ,  B01L2300/0645 ,  B82Y30/00 ,  C12Q1/001 ,  G01N27/3277 ,  G01N33/5436 ,  G01N33/5438

摘要： An embodiment of the invention relates to a biochip comprising at least two measurement electrodes, a synthesis electrode, a ground electrode, a gap between the at least two measurement electrodes, a porous dielectric isolation layer and a gel comprising a probe in the gap, wherein the porous dielectric isolation layer is between the synthesis electrode and the gel. Yet other embodiments relate to the method of manufacturing the biochip and using the biochip for electrical detection of bio-species.

摘要翻译： 本发明的实施例涉及一种生物芯片，其包括至少两个测量电极，合成电极，接地电极，至少两个测量电极之间的间隙，多孔电介质隔离层和在间隙中包含探针的凝胶，其中 多孔介电隔离层位于合成电极和凝胶之间。 其他实施方案涉及制造生物芯片的方法，并且使用用于生物物种的电检测的生物芯片。

公开(公告)号：US07470620B2

公开(公告)日：2008-12-30

申请号：US12023867

申请日：2008-01-31

申请人： Valery M. Dubin ,  Mark Bohr

发明人： Valery M. Dubin ,  Mark Bohr

IPC分类号： H01L21/44

CPC分类号： H01L29/76 ,  B82Y10/00 ,  H01L21/768 ,  H01L21/76879 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/53276 ,  H01L29/66439 ,  H01L29/7613 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of methods in accordance with the present invention provide three-dimensional carbon nanotube (CNT) integrated circuits comprising layers of arrays of CNT's separated by dielectric layers with conductive traces formed within the dielectric layers to electrically interconnect individual CNT's. The methods to fabricate three-dimensional carbon nanotube FET integrated circuits include the selective deposition of carbon nanotubes onto catalysts selectively formed on a conductive layer at the bottom of openings in a dielectric layer. The openings in the dielectric layer are formed using suitable techniques, such as, but not limited to, dielectric etching, and the formation of ring gate electrodes, including spacers, that provide openings for depositing self-aligned carbon nanotube semiconductor channels.

公开(公告)号：US20080157212A1

公开(公告)日：2008-07-03

申请号：US11647893

申请日：2006-12-28

申请人： Adrien R. Lavoie ,  Valery M. Dubin ,  John J. Plombon ,  Juan E. Dominguez ,  Harsono S. Simka ,  Joseph H. Han ,  Mark Doczy

发明人： Adrien R. Lavoie ,  Valery M. Dubin ,  John J. Plombon ,  Juan E. Dominguez ,  Harsono S. Simka ,  Joseph H. Han ,  Mark Doczy

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L21/28

CPC分类号： H01L21/823842 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/7833

摘要： Described herein are metal gate electrode stacks including a low resistance metal cap in contact with a metal carbonitride diffusion barrier layer, wherein the metal carbonitride diffusion barrier layer is tuned to a particular work function to also serve as a work function metal for a pMOS transistor. In an embodiment, the work function-tuned metal carbonitride diffusion barrier prohibits a low resistance metal cap layer of the gate electrode stack from migrating into the MOS junction. In a further embodiment of the present invention, the work function of the metal carbonitride barrier film is modulated to be p-type with a pre-selected work function by altering a nitrogen concentration in the film.

摘要翻译： 这里描述的金属栅极电极堆叠包括与金属碳氮化物扩散阻挡层接触的低电阻金属帽，其中金属碳氮化物扩散阻挡层被调谐到特定的功函数，以用作pMOS晶体管的功函数金属。 在一个实施例中，工作功能调谐金属碳氮化物扩散屏障禁止栅电极堆叠的低电阻金属盖层迁移到MOS结。 在本发明的另一个实施方案中，金属碳氮化物阻挡膜的功函数通过改变膜中的氮浓度而被调制为具有预选功函的p型。

公开(公告)号：US07372165B2

公开(公告)日：2008-05-13

申请号：US11077252

申请日：2005-03-09

申请人： Valery M. Dubin ,  Ramanan V. Chebiam

发明人： Valery M. Dubin ,  Ramanan V. Chebiam

IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

摘要翻译： 描述了具有导电材料可靠性增加的半导体器件的半导体器件的方法和装置。 该方法和装置包括在衬底上形成导电路径。 由第一材料制成的导电路径。 然后将第二材料沉积在导电路径上。 一旦第二材料沉积在导电路径上，则促进了第二材料进入导电路径的扩散。 第二材料具有预定的溶解度以基本上扩散到第一材料内的晶界。

公开(公告)号：US07338585B2

公开(公告)日：2008-03-04

申请号：US11383925

申请日：2006-05-17

申请人： Rohan N. Akolkar ,  Valery M. Dubin

发明人： Rohan N. Akolkar ,  Valery M. Dubin

IPC分类号： C25D5/02 ,  C25D7/12 ,  C25D3/38

CPC分类号： C25D3/38 ,  H01L21/2885 ,  H01L21/76879

摘要： A method comprising forming an interconnection opening through a dielectric material to a contact point; and electroplating a interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine. A method comprising forming an interconnection opening through a dielectric material to a contact point; lining the interconnection opening with a barrier layer and a seed layer; and electroplating an interconnection comprising copper in the contact opening using an electroplating bath comprising an alkoxylated sulfopropylated alkylamine.

摘要翻译： 一种方法，包括通过介电材料形成到接触点的互连开口; 以及使用包含烷氧基化磺丙基化烷基胺的电镀浴在接触开口中电镀包含铜的互连。 一种方法，包括通过介电材料形成到接触点的互连开口; 用隔离层和种子层对互连开口进行衬里; 以及使用包含烷氧基化磺丙基化烷基胺的电镀浴在接触开口中电镀包含铜的互连。

公开(公告)号：US07316061B2

公开(公告)日：2008-01-08

申请号：US10357927

申请日：2003-02-03

申请人： Valery M. Dubin ,  Thomas S. Dory

发明人： Valery M. Dubin ,  Thomas S. Dory

IPC分类号： H05K3/36

CPC分类号： H01L23/373 ,  B82Y10/00 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73253 ,  H01L2924/01037 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/16195 ,  Y10S977/732 ,  Y10S977/744 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T428/30

摘要： According to one aspect of the invention, a method of constructing an electronic assembly is provided. A layer of metal is formed on a backside of a semiconductor wafer having integrated formed thereon. Then, a porous layer is formed on the metal layer. A barrier layer of the porous layer at the bottom of the pores is thinned down. Then, a catalyst is deposited at the bottom of the pores. Carbon nanotubes are then grown in the pores. Another layer of metal is then formed over the porous layer and the carbon nanotubes. The semiconductor wafer is then separated into microelectronic dies. The dies are bonded to a semiconductor substrate, a heat spreader is placed on top of the die, and a semiconductor package resulting from such assembly is sealed. A thermal interface is formed on the top of the heat spreader. Then a heat sink is placed on top of the thermal interface.

公开(公告)号：US07300860B2

公开(公告)日：2007-11-27

申请号：US10814375

申请日：2004-03-30

申请人： Valery M. Dubin

发明人： Valery M. Dubin

IPC分类号： H01L21/20 ,  H01L21/44 ,  H01L23/48

CPC分类号： B82Y10/00 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/53276 ,  H01L2221/1094 ,  H01L2924/0002 ,  Y10S977/847 ,  Y10S977/857 ,  Y10S977/936 ,  H01L2924/00

摘要： A method of fabricating an integrated circuit comprises forming or providing a solution containing carbon nanotubes and forming a metal layer utilizing the solution.

摘要翻译： 制造集成电路的方法包括使用该溶液形成或提供含有碳纳米管的溶液并形成金属层。

公开(公告)号：US07279231B2

公开(公告)日：2007-10-09

申请号：US10649087

申请日：2003-08-26

申请人： Ramanan V. Chebiam ,  Valery M. Dubin

发明人： Ramanan V. Chebiam ,  Valery M. Dubin

IPC分类号： B32B15/04 ,  B32B15/20 ,  H01L21/445 ,  H01L29/43

CPC分类号： C23C18/50 ,  C23C18/34 ,  C23C18/40 ,  C23C18/44 ,  C23C18/48 ,  C23C18/52 ,  Y10T428/12861 ,  Y10T428/12875 ,  Y10T428/12889 ,  Y10T428/12896 ,  Y10T428/12903 ,  Y10T428/1291 ,  Y10T428/12944

摘要： The present invention relates to a cobalt electroless plating bath composition. In one embodiment, the present invention relates to cobalt electroless plating in the fabrication of interconnect structures in semiconductor devices.

摘要翻译： 本发明涉及一种钴化学镀浴组合物。 在一个实施例中，本发明涉及在半导体器件中的互连结构的制造中的钴无电解电镀。