公开(公告)号：US09793206B1

公开(公告)日：2017-10-17

申请号：US15280518

申请日：2016-09-29

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. DeProspo ,  Huai Huang ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L21/76865 ,  H01L21/321 ,  H01L21/76816 ,  H01L21/76828 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76877 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53242 ,  H01L23/53257

Abstract: A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width. The method also includes forming a second trench in the substrate, which has a second width that is greater than the first width. The method also includes depositing a metal layer into the trenches, applying a dielectric over the metal, and diffusing metal atoms from the trenches to the dielectric. The dielectric absorbs a majority of the metal atoms from the first trench while simultaneously absorbing only a minority of metal atoms from the second trench.

公开(公告)号：US20170278788A1

公开(公告)日：2017-09-28

申请号：US15479983

申请日：2017-04-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Christopher J. Penny ,  Michael Rizzolo

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths; and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.

公开(公告)号：US09760817B2

公开(公告)日：2017-09-12

申请号：US15212803

申请日：2016-07-18

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. DeProspo ,  Michael Rizzolo

IPC: G06K19/06 ,  G06K19/04 ,  C23C14/22

CPC classification number: G07C9/00007 ,  C23C14/22 ,  G06K7/1417 ,  G06K19/048 ,  G06K19/06037 ,  G06K19/06178 ,  G07C9/00658 ,  G07C9/00714 ,  G07C9/00722

Abstract: An aspect of the disclosure includes a security system and method having a key with nanoscale features. The key includes a body. At least one pattern member disposed on the body, the pattern member formed using a directed self-assembly polymer to define a pattern of random feature structures thereon, the feature structures having a width of less than 100 nanometers.

公开(公告)号：US20170221285A1

公开(公告)日：2017-08-03

申请号：US15164136

申请日：2016-05-25

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Bartlet H. DeProspo ,  Michael Rizzolo

IPC: G07C9/00 ,  G06K7/14 ,  G06K19/06

CPC classification number: G07C9/00007 ,  C23C14/22 ,  G06K7/1417 ,  G06K19/048 ,  G06K19/06037 ,  G06K19/06178 ,  G07C9/00658 ,  G07C9/00714 ,  G07C9/00722

Abstract: An aspect of the disclosure includes a security system and method having a key with nanoscale features. The key includes a body. At least one pattern member disposed on the body, the pattern member formed using a directed self-assembly polymer to define a pattern of random feature structures thereon, the feature structures having a width of less than 100 nanometers.

公开(公告)号：US20170213470A1

公开(公告)日：2017-07-27

申请号：US15008028

申请日：2016-01-27

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Jonathan H. Connell, II ,  Nalini K. Ratha ,  Michael Rizzolo

IPC: G09B5/12 ,  A61B5/11 ,  A61B5/00 ,  A61B5/01

CPC classification number: G09B5/125 ,  A61B5/02055 ,  A61B5/1118 ,  A61B5/4806 ,  A61B5/486 ,  A61B5/681 ,  A61B5/6898 ,  A61B2560/0247 ,  G09B19/0038

Abstract: Techniques for motivating a user during a workout using different coaching styles are provided. In one aspect, a method for motivational coaching of a user during workout sessions includes the steps of: selecting a coaching style for the user based on input from the user and from coaching styles used for at least one other user; determining, during a workout session, whether the coaching style should be changed to enhance performance of the user based on data obtained from the user via a mobile device worn by the user; changing the coaching style if it is determined that the coaching style should be changed to enhance performance of the user; continuing with a current coaching style if it is determined that the coaching style should not be changed; and providing feedback to the user during the workout session based on the coaching style.

公开(公告)号：US09685406B1

公开(公告)日：2017-06-20

申请号：US15131157

申请日：2016-04-18

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Elbert E. Huang ,  Raghuveer R. Patlolla ,  Cornelius B. Peethala ,  David L. Rath ,  Hosadurga Shobha

IPC: H01L21/4763 ,  H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/53295

Abstract: A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer, conformally depositing a barrier layer on the dielectric layer and on sides and a bottom of each one of the plurality of openings, depositing a contact layer on the barrier layer in each one of the plurality of openings, removing a portion of each contact layer from each one of the plurality of openings, and removing a portion of the barrier layer from each one of the plurality of openings, wherein at least the removal of the portion of the barrier layer is performed using an etchant including: (a) a compound selected from group consisting of -azole, -triazole, and combinations thereof; (b) a compound containing one or more peroxy groups; (c) one or more alkaline metal hydroxides; and (d) water.

公开(公告)号：US20170125302A1

公开(公告)日：2017-05-04

申请号：US15400643

申请日：2017-01-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Jay W. Strane

IPC: H01L21/8234 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/31051 ,  H01L21/31055 ,  H01L21/31056 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76229 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66795

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in the narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

公开(公告)号：US09583498B2

公开(公告)日：2017-02-28

申请号：US15193545

申请日：2016-06-27

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo

IPC: H01L21/82 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/66

CPC classification number: H01L27/11521 ,  G11C13/0011 ,  H01L27/2463 ,  H01L29/4236 ,  H01L29/66825 ,  H01L29/788 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: An exposed edge of a conductive liner in a Damascene trench provides a high aspect ratio geometry of a non-volatile memory cell that can be scaled to arbitrarily small and nanoscale areas and thus provides an extremely compact non-volatile memory array layout that is applicable to any non-volatile memory technology such as resistive memory (RRAM), magnetic memory (MRAM), phase change memory (PCRAM) and the like. The high aspect ratio of the non-volatile memory cell area offsets the sharp increase in filament forming voltage required in conductive bridge memories (CBRAMs) as the non-volatile memory cells are scaled to very small sizes. The compact memory cell layout is also tolerant of lithographic overlay errors and provides a high degree of uniformity of electrical characteristics which are tunable by maskless and non-lithographic processes.

Abstract translation: 在大马士革沟槽中的导电衬垫的暴露边缘提供非易失性存储器单元的高纵横比几何形状，其可以缩放到任意小的和纳米尺度的区域，并且因此提供非常紧凑的非易失性存储器阵列布局，其适用于 诸如电阻存储器（RRAM），磁存储器（MRAM），相变存储器（PCRAM）等的任何非易失性存储器技术。 当非易失性存储器单元被缩放到非常小的尺寸时，非易失性存储单元区域的高纵横比抵消导电桥式存储器（CBRAM）中所需的灯丝形成电压的急剧增加。 紧凑的存储单元布局还容许光刻重叠误差，并且提供通过无掩模和非平版印刷工艺可调谐的电特性的高度均匀性。

公开(公告)号：US09548243B1

公开(公告)日：2017-01-17

申请号：US14755647

申请日：2015-06-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Michael Rizzolo ,  Terry A. Spooner ,  Theodorus E. Standaert

IPC: H01L21/768 ,  H01L21/31 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/76816 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329

Abstract: A method of forming via openings that includes forming sidewall spacers on a plurality of mandrels that are overlying a hardmask layer that is present on an interlevel dielectric layer. Etching the hardmask layer using a portion of the sidewall spacers and the plurality of mandrels to form a first pillar of hardmask material. The interlevel dielectric layer is etched using the first pillar of hardmask material as a mask to define a first via opening. The plurality of mandrels are removed. The hardmask layer is etched using the spacers to define a second pillar of hardmask material. The interlevel dielectric layer is etched using the second pillar of hardmask material to provide a second via opening.

Abstract translation: 一种形成通孔的方法，其包括在层叠介电层上存在的硬掩模层上的多个心轴上形成侧壁间隔物。 使用侧壁间隔件和多个心轴的一部分来蚀刻硬掩模层以形成硬掩模材料的第一支柱。 使用硬掩模材料的第一柱作为掩模蚀刻层间电介质层以限定第一通孔。 多个心轴被移除。 使用间隔物蚀刻硬掩模层以限定硬掩模材料的第二支柱。 使用硬掩模材料的第二柱蚀刻层间电介质层以提供第二通孔。

公开(公告)号：US11869783B2

公开(公告)日：2024-01-09

申请号：US17244084

申请日：2021-04-29

Applicant: International Business Machines Corporation

Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert ,  James Stathis

IPC: H01L21/67 ,  G06N5/04 ,  G06N20/00

CPC classification number: H01L21/67271 ,  G06N5/04 ,  G06N20/00

Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.