公开(公告)号：US20170309587A1

公开(公告)日：2017-10-26

申请号：US15643906

申请日：2017-07-07

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/17 ,  H01L23/49838 ,  H01L23/5227 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

公开(公告)号：US20170031095A1

公开(公告)日：2017-02-02

申请号：US15188914

申请日：2016-06-21

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Shinichi WATANUKI

IPC: G02B6/122 ,  G02B6/132 ,  G02F1/025 ,  G02B6/12

CPC classification number: G02B6/122 ,  G02B6/12004 ,  G02B6/132 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02F1/025 ,  G02F2001/0152 ,  G02F2202/103 ,  G02F2202/104 ,  H01L31/0248

Abstract: An SOI substrate includes a base substrate, a polycrystalline silicon layer formed on the base substrate, an insulating layer formed on the polycrystalline silicon layer, and a semiconductor layer formed on the insulating layer, and optical waveguides are formed in the semiconductor layer of the SOI substrate. Thus, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin. Since the polycrystalline silicon layer includes a plurality of grains (amass of grains made of a single crystal Si), even when leakage of light is generated beyond the insulating layer, reflection (diffusion) of light can be suppressed. In addition, by arranging the polycrystalline silicon layer under the insulating layer, the insulating layer can be made thin, so that distortion of a substrate can be suppressed.

Abstract translation: SOI基板包括基底基板，形成在基底基板上的多晶硅层，形成在多晶硅层上的绝缘层，以及形成在绝缘层上的半导体层，在SOI的半导体层中形成光波导 基质。 因此，通过将多晶硅层配置在绝缘层的下方，可以使绝缘层变薄。 由于多晶硅层包括多个晶粒（由单晶Si制成的晶粒的淀积），所以即使在超过绝缘层的情况下产生光的泄漏，也可以抑制光的反射（扩散）。 此外，通过将多晶硅层设置在绝缘层的下方，可以使绝缘层变薄，从而能够抑制基板的变形。

公开(公告)号：US20170006007A1

公开(公告)日：2017-01-05

申请号：US15155854

申请日：2016-05-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA

IPC: H04L29/06 ,  H04W12/06 ,  H04W4/00

CPC classification number: H04W4/80 ,  H04W12/06

Abstract: A semiconductor device that can perform high speed data communication is provided.The semiconductor device includes a communication chip that performs authentication processing that determines whether or not data communication can be performed with an external device and performs the data communication with the external device when the authentication processing is successfully performed and a control chip that performs data processing of transmission/reception of the data communication through the communication chip. The communication chip includes a first memory that stores authentication data for the authentication processing. The control chip includes a second memory for the data processing.

Abstract translation: 该半导体装置包括通信芯片，其进行认证处理，该认证处理确定在成功执行认证处理时是否可以与外部设备进行数据通信，并执行与外部设备的数据通信;以及控制芯片，其执行数据处理 通过通信芯片发送/接收数据通信。 通信芯片包括存储用于认证处理的认证数据的第一存储器。 控制芯片包括用于数据处理的第二存储器。

公开(公告)号：US20160181354A1

公开(公告)日：2016-06-23

申请号：US15058589

申请日：2016-03-02

Applicant: Renesas Electronics Corporation

Inventor： Yoshiyuki SATO ,  Yasutaka NAKASHIBA

IPC: H01L29/06 ,  H01L23/528 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L23/528 ,  H01L28/20 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/405 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device in which the concentration of an electric field is suppressed in a region overriding a drain region and a source region. A drain region is formed in a first region, a source region is formed in a second region. A field oxide film surrounds the first region in a plan view. A metal interconnect situated over a field oxide film. The metal interconnect formed of a metal having an electric resistivity at 25° C. of 40 μΩ·cm or more and 200 μΩ·cm or less. Further, the metal interconnect is repeatedly provided spirally in a direction along the edges of the first region. Further, the metal interconnect is electrically connected at the innermost circumference with the drain region, and is connected at the outermost circumference to the source region or a ground potential.

公开(公告)号：US20150263002A1

公开(公告)日：2015-09-17

申请号：US14727446

申请日：2015-06-01

Applicant: Renesas Electronics Corporation

Inventor： Akira MATSUMOTO ,  Yoshinao MIURA ,  Yasutaka NAKASHIBA

IPC: H01L27/088 ,  H01L23/492 ,  H01L27/06 ,  H01L23/528 ,  H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49562 ,  H01L23/4824 ,  H01L23/485 ,  H01L23/492 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0203 ,  H01L27/0605 ,  H01L27/088 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/78 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/4805 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1033 ,  H01L2924/10344 ,  H01L2924/13064 ,  H01L2924/30101 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction (Y direction in the view), each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.

Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿着第一方向（视图中的Y方向）并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。

公开(公告)号：US20150061660A1

公开(公告)日：2015-03-05

申请号：US14475623

申请日：2014-09-03

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu NEMOTO ,  Yasutaka NAKASHIBA ,  Takasuke HASHIMOTO ,  Shinichi UCHIDA ,  Kazunori GO ,  Hiroshi OE ,  Noriko YOSHIKAWA

IPC: G01R21/00 ,  H01F21/00

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.

Abstract translation: 传感器装置包括电力线和半导体器件。 半导体器件包括电感器。 使用互连层（稍后将使用图3描述）形成电感器。 当从垂直于半导体器件的方向观察时，电源线和半导体器件彼此重叠。 半导体器件包括两个电感器。 当从垂直于半导体器件的方向观察时，电力线在两个电感器之间延伸。

公开(公告)号：US20140374876A1

公开(公告)日：2014-12-25

申请号：US14483300

申请日：2014-09-11

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L24/17 ,  H01L23/49838 ,  H01L23/5227 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1713 ,  H01L2224/81385 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device is provided with a semiconductor chip. The semiconductor chip has a semiconductor substrate, an interconnect layer, an inductor and conductive pads (first pads). The interconnect layer is provided on the semiconductor substrate. The interconnect layer includes the inductor. The pads are provided on the interconnect layer. The pads are provided in a region within a circuit forming region of the semiconductor chip, which does not overlap the inductor.

Abstract translation: 半导体器件设置有半导体芯片。 半导体芯片具有半导体衬底，互连层，电感器和导电焊盘（第一焊盘）。 互连层设置在半导体衬底上。 互连层包括电感器。 焊盘设置在互连层上。 焊盘设置在不与电感器重叠的半导体芯片的电路形成区域内的区域中。

公开(公告)号：US20140264722A1

公开(公告)日：2014-09-18

申请号：US14209384

申请日：2014-03-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Yutaka Akiyama

IPC: H01L27/12

CPC classification number: H01L27/0688 ,  H01L23/49541 ,  H01L23/5227 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00014

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

Abstract translation: 半导体芯片包括具有不同参考电位的第一电路和第二电路。 作为第一电路的基准电位的第一电位通过多个引线端子中的任一个施加到半导体芯片，作为第二电路的基准电位的第二电位通过多个引线端子中的任一个施加到半导体芯片 。 半导体芯片的基板具有其中掩埋绝缘层和第一导电类型的半导体层层叠在诸如SOI衬底的半导体衬底上的结构。 通过管芯焊盘和用于衬底电位的引线端子将固定电位施加到半导体衬底。 通过与第一电路的参考电位和第二电路的参考电位的不同路径将固定电位施加到半导体芯片。

公开(公告)号：US20240170463A1

公开(公告)日：2024-05-23

申请号：US18511547

申请日：2023-11-16

Applicant: Renesas Electronics Corporation

Inventor： Takayuki IGARASHI ,  Yasutaka NAKASHIBA

IPC: H01L25/10 ,  H01L23/522 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/105 ,  H01L23/5227 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137

Abstract: A second distance between a second lower inductor and a second upper inductor, which are components of a second transformer is smaller than a first distance between a first lower inductor and a first upper inductor which are components of a first transformer.

公开(公告)号：US20240145553A1

公开(公告)日：2024-05-02

申请号：US18051935

申请日：2022-11-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Makoto KOSHIMIZU ,  Yasutaka NAKASHIBA ,  Tohru KAWAI

IPC: H01L29/40 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/402 ,  H01L29/401 ,  H01L29/66681 ,  H01L29/7816

Abstract: LDMOS having an n-type source region and a drain region formed on an upper surface of a semiconductor substrate, a gate electrode formed on the semiconductor substrate via a gate dielectric film, and a field plate electrode formed on the semiconductor substrate between the gate electrode and the drain region via a dielectric film having a larger film thickness than the gate dielectric film, is formed. Here, the field plate electrode has a larger work function than an n-type semiconductor region formed in the semiconductor substrate directly below the field plate electrode.