公开(公告)号：US20150348640A1

公开(公告)日：2015-12-03

申请号：US14724229

申请日：2015-05-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/26 ,  H01L21/28 ,  H01L27/115 ,  G11C16/14 ,  G11C16/04

CPC classification number: G11C16/26 ,  G11C16/0408 ,  G11C16/0433 ,  G11C16/0441 ,  G11C16/08 ,  G11C16/14 ,  H01L21/0276 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/11521 ,  H01L27/11524

Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.

Abstract translation: 本公开涉及一种半导体衬底上的非易失性存储单元，包括：第一晶体管，包括控制栅极，浮置栅极和漏极区域;第二晶体管，包括控制栅极，浮置栅极和漏极区域， 其中第一和第二晶体管的浮置栅极电耦合，并且第二晶体管包括电耦合到其漏极区域并且通过隧道电介质层与其浮动栅极相对延伸的导电区域。

公开(公告)号：US20150325581A1

公开(公告)日：2015-11-12

申请号：US14806432

申请日：2015-07-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Arnaud Regnier ,  Stephan Niel ,  Francesco La Rosa

IPC: H01L27/115 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/823468 ,  H01L21/26513 ,  H01L21/28273 ,  H01L21/823425 ,  H01L21/823443 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L29/4236 ,  H01L29/4975 ,  H01L29/6656 ,  H01L29/66613 ,  H01L29/66825 ,  H01L29/772 ,  H01L29/7881

Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.

Abstract translation: 集成电路形成在半导体衬底上，并且包括沟槽导体和形成在衬底表面上的第一晶体管。 晶体管包括：晶体管栅极结构，在栅极结构的第一边缘和沟槽导体的上边缘之间的衬底中延伸的第一掺杂区域和形成在栅极结构的第一边缘上方的第一间隔区， 第一掺杂区域。 第一间隔物完全覆盖第一掺杂区域，并且硅化物存在于沟槽导体上，但不存在于第一掺杂区域的表面上。

公开(公告)号：US09110116B2

公开(公告)日：2015-08-18

申请号：US14494095

申请日：2014-09-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Pascal Fornara

IPC: H01L23/58 ,  G01R27/26 ,  G11C27/02 ,  H01L21/84 ,  H01L23/522 ,  H01L27/08 ,  H01L27/12 ,  H01L49/02 ,  H01L29/94 ,  G04F13/00 ,  G01R17/02 ,  G11C11/24 ,  H01G4/005 ,  H01G4/018 ,  H01G4/38

CPC classification number: G01R27/2605 ,  G01R17/02 ,  G04F10/10 ,  G04F13/00 ,  G11C11/24 ,  G11C27/024 ,  H01G4/005 ,  H01G4/018 ,  H01G4/38 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

Abstract translation: 一种用于时间测量的电荷流动电路，包括电串联的多个基本电容元件，每个元件电容元件通过其介电空间泄漏。

公开(公告)号：US09076878B2

公开(公告)日：2015-07-07

申请号：US14043718

申请日：2013-10-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier ,  Yoann Goasduff

IPC: H01L21/336 ,  H01L29/788 ,  H01L29/66 ,  G11C16/04 ,  H01L27/115 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/788 ,  G11C16/0433 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/4175 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/7827

Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.

Abstract translation: 本公开涉及一种用于在半导体衬底上制造非易失性存储器的方法，包括以下步骤：在衬底的深度中注入形成选择晶体管的源极区的第一掺杂区，在衬底中形成掩埋栅，包括 在衬底的上表面和第一掺杂区之间延伸的深部分，埋入掩埋栅的两个相邻深部之间，形成一对存储单元的公共选择晶体管的公共漏极区的第二掺杂区，选择晶体管 因此具有在第一掺杂区域和第二掺杂区域之间延伸的沟道区域的一对存储单元，沿着与相邻两个深部分的两个掩埋栅极相对的面以及沿掩埋栅极的相对的上边缘注入，形成源极区域的第三掺杂区域 的电荷累积晶体管。

公开(公告)号：US08830761B2

公开(公告)日：2014-09-09

申请号：US13786202

申请日：2013-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C11/56 ,  G11C8/12

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。

公开(公告)号：US12244228B2

公开(公告)日：2025-03-04

申请号：US18187831

申请日：2023-03-22

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics S.r.l.

Inventor： Francesca Grande ,  Francesco La Rosa ,  Maria Giaquinta ,  Alfredo Signorello

IPC: H02M3/07 ,  G11C16/30 ,  H02M1/08 ,  G11C16/10

Abstract: In an embodiment a device includes a supply node configured to receive a supply voltage, an output node configured to provide an output voltage, a plurality of switching stages coupled to the supply node and to the output node, a sensing circuit coupled to the supply node and configured to provide at least one sensing signal based on the supply voltage and a driver circuit coupled to the sensing circuit and to the plurality of switching stages, wherein the driver circuit is configured to provide the drive signal based on at least one sensing signal exceeding or failing to exceed at least one reference voltage level and to selectively bypass a selected number of the plurality of switching stages based on the drive signal thereby varying an output voltage level at the output node.

公开(公告)号：US12230357B2

公开(公告)日：2025-02-18

申请号：US17902171

申请日：2022-09-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C7/10 ,  G11C7/22 ,  H03K5/135 ,  H03K5/1534

Abstract: The present description concerns an electronic device including: a first input configured to receive a clock signal, coupled by a first input buffer to a first circuit; and at least an output coupled by an output buffer to the first circuit, the output buffer being synchronized on first edges of the clock signal, wherein the first input buffer includes a data input coupled to the first input and is configured to maintain the value on its output constant whatever the value on its data input during a duration following each first edge of the clock signal.

公开(公告)号：US12174909B2

公开(公告)日：2024-12-24

申请号：US17373935

申请日：2021-07-13

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Antonino Conte

IPC: G06F17/15 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G06N3/02 ,  H03K19/20

Abstract: In an embodiment a method programming floating gate transistors belonging to non-volatile memory cells to multilevel threshold voltages respectively corresponding to the weight factors, performing a sensing operation of the programmed floating gate transistors with a control signal adapted to make the corresponding memory cells become conductive at an instant determined by a respective programmed threshold voltage, performing the convolutional computation by using the input values during an elapsed time for each memory cell to become conductive and outputting output values resulting from the convolutional computation.

公开(公告)号：US20230015627A1

公开(公告)日：2023-01-19

申请号：US17812127

申请日：2022-07-12

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics International N.V.

Inventor： Francesco La Rosa ,  Marco Bildgen

IPC: H03K19/17768 ,  H03K19/1776 ,  H03K19/08

Abstract: In an embodiment an integrated device includes a first physical unclonable function module configured to generate an initial data group and management module configured to generate an output data group from at least the initial data group, authorize only D successive deliveries of the output data group on a first output interface of the device, D being a non-zero positive integer, and prevent any new generation of the output data group.

公开(公告)号：US20200274722A1

公开(公告)日：2020-08-27

申请号：US16783631

申请日：2020-02-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Marc Mantelli ,  Stephan Niel ,  Arnaud Regnier

IPC: H04L9/32 ,  G06F21/72 ,  G06F21/60 ,  G11C16/04 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30

Abstract: In accordance with an embodiment, a physically unclonable function device includes a set of transistor pairs, transistors of the set of transistor pairs having a randomly distributed effective threshold voltage belonging to a common random distribution; a differential read circuit configured to measure a threshold difference between the effective threshold voltages of transistors of transistor pairs of the set of transistor pairs, and to identify a transistor pair in which the measured threshold difference is smaller than a margin value as being an unreliable transistor pair; and a write circuit configured to shift the effective threshold voltage of a transistor of the unreliable transistor pair to be inside the common random distribution.