公开(公告)号：US20060234167A1

公开(公告)日：2006-10-19

申请号：US11452830

申请日：2006-06-13

申请人： Trung Doan ,  Terry Gilton

发明人： Trung Doan ,  Terry Gilton

IPC分类号： G03F7/40

CPC分类号： G03F7/322 ,  G03F7/36

摘要： The invention includes a process whereby a solvent is utilized to remove soluble portions of a resist, and subsequently the solvent can be removed with a gas-fortified liquid. In particular aspects, the gas-fortified liquid emits bubbles during the removal of the solvent. Additionally, the gas-fortified liquid can be utilized to remove residual resist scum, and in such aspects the gas-fortified liquid can emit bubbles during the scum removal.

摘要翻译： 本发明包括使用溶剂去除抗蚀剂的可溶部分的方法，随后用气体强化液体除去溶剂。 在特定方面，气体强化液体在除去溶剂期间会发出气泡。 此外，气体强化液体可用于去除残留的抗蚀剂浮渣，并且在这些方面，气体强化液体可以在浮渣期间发出气泡。

公开(公告)号：US20060157721A1

公开(公告)日：2006-07-20

申请号：US11032853

申请日：2005-01-11

申请人： Chuong Tran ,  Trung Doan

发明人： Chuong Tran ,  Trung Doan

IPC分类号： H01L33/00 ,  H01L21/00

CPC分类号： H01L33/505 ,  H01L33/0079 ,  H01L33/44 ,  H01L33/641 ,  H01L2224/48091 ,  H01L2224/4918 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/12041 ,  H01L2924/00014

摘要： A vertical light emitting diode (LED) includes a metal substrate; a p-electrode coupled to the metal substrate; a p-contact coupled to the p-electrode; a p-GaN portion coupled to the p electrode; an active region coupled to the p-GaN portion; an n-GaN portion coupled to the active region; and a phosphor layer coupled to the n-GaN.

摘要翻译： 垂直发光二极管（LED）包括金属基板; 耦合到所述金属基板的p电极; 耦合到p电极的p型触点; 耦合到p电极的p-GaN部分; 耦合到p-GaN部分的有源区; 耦合到有源区的n-GaN部分; 和与n-GaN耦合的磷光体层。

公开(公告)号：US20060154391A1

公开(公告)日：2006-07-13

申请号：US11032880

申请日：2005-01-11

申请人： Chuong Tran ,  Trung Doan

发明人： Chuong Tran ,  Trung Doan

IPC分类号： H01L21/00

CPC分类号： H01L33/22 ,  H01L33/0095

摘要： Systems and methods are disclosed for fabricating a semiconductor light emitting diode (LED) device by forming an n-gallium nitride (n-GaN) layer on the LED device; and roughening the surface of the n-GaN layer to extract light from an interior of the LED device.

摘要翻译： 公开了通过在LED器件上形成n-氮化镓（n-GaN）层来制造半导体发光二极管（LED）器件的系统和方法; 并且使n-GaN层的表面变粗糙以从LED器件的内部提取光。

公开(公告)号：US20060154390A1

公开(公告)日：2006-07-13

申请号：US11032854

申请日：2005-01-11

申请人： Chuong Tran ,  Trung Doan

发明人： Chuong Tran ,  Trung Doan

IPC分类号： H01L21/00

CPC分类号： B23K26/40 ,  H01L33/0095

摘要： Systems and methods are disclosed for producing vertical LED array on a metal substrate; evaluating said array of LEDs for defects; destroying one or more defective LEDs; forming good LEDs only LED array suitable for wafer level package.

摘要翻译： 公开了用于在金属基板上产生垂直LED阵列的系统和方法; 评估所述LED阵列的缺陷; 破坏一个或多个有缺陷的LED; 仅形成适合晶圆级封装的LED阵列。

公开(公告)号：US20060144333A1

公开(公告)日：2006-07-06

申请号：US11364738

申请日：2006-02-28

申请人： Trung Doan ,  Gurtej Sandhu

发明人： Trung Doan ,  Gurtej Sandhu

IPC分类号： C23C16/00

CPC分类号： C23C16/45544 ,  C23C16/4412 ,  C30B25/02 ,  H01L21/67017

摘要： An atomic layer deposition method includes positioning a semiconductor substrate within an atomic layer deposition chamber. A first deposition precursor is fed to the chamber under first vacuum conditions effective to form a first monolayer on the substrate. The first vacuum conditions are maintained at least in part by a first non-roughing vacuum pump connected to the chamber and through which at least some of the first deposition precursor flows. After forming the first monolayer, a purge gas is fed to the chamber under second vacuum conditions maintained at least in part by a second non-roughing vacuum pump connected to the chamber which is different from the first non-roughing vacuum pump and through which at least some of the purge gas flows. An atomic layer deposition apparatus is disclosed.

公开(公告)号：US20060115987A1

公开(公告)日：2006-06-01

申请号：US11331573

申请日：2006-01-13

申请人： Trung Doan ,  Tyler Lowrey

发明人： Trung Doan ,  Tyler Lowrey

IPC分类号： H01L21/461

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7881

摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

摘要翻译： 提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。 该器件包括具有电隔离的有源区的硅衬底。 栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。 通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。 然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。 在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。

公开(公告)号：US20060076040A1

公开(公告)日：2006-04-13

申请号：US11290339

申请日：2005-11-30

申请人： Scott Moore ,  Trung Doan

发明人： Scott Moore ,  Trung Doan

IPC分类号： B08B3/00 ,  B24B9/00 ,  B08B3/04

CPC分类号： H01L21/6704 ,  B08B1/00 ,  B08B7/0092 ,  B24B37/042 ,  H01L21/67046 ,  Y10S134/902 ,  Y10S438/906 ,  Y10S438/959 ,  Y10S438/963 ,  Y10S438/974

摘要： In one aspect, the invention includes a method of treating a surface of a substrate. A mixture which comprises at least a frozen first material and liquid second material is provided on the surface and moved relative to the substrate. In another aspect, the invention encompasses a method of treating a plurality of substrates. A treating member is provided proximate a first substrate, and an initial layer of frozen material is formed over a surface of the treating member. A surface of the first substrate is treated by moving at least one of the treating member and the first substrate relative to the other of the treating member and the first substrate. After the surface of the first substrate is treated, the initial layer of frozen material is removed from over the surface of the treating member. The treating member is then provided proximate another substrate, and the surface of the other substrate is treated by moving at least one of the treating member and the second substrate relative to the other of the treating member and the second substrate.

摘要翻译： 一方面，本发明包括处理基材表面的方法。 至少包含冷冻第一材料和液体第二材料的混合物设置在表面上并相对于基底移动。 另一方面，本发明包括一种处理多个基底的方法。 处理构件设置在第一基底附近，并且在处理构件的表面上形成初始冷冻材料层。 通过相对于处理构件和第一基板中的另一个移动处理构件和第一基板中的至少一个来处理第一基板的表面。 在处理第一基板的表面之后，从处理构件的表面上去除初始的冷冻材料层。 然后将治疗构件设置在另一基底附近，并且通过相对于处理构件和第二基底中的另一个移动处理构件和第二基底中的至少一个来处理另一基底的表面。

公开(公告)号：US20060006520A1

公开(公告)日：2006-01-12

申请号：US11208304

申请日：2005-08-19

申请人： Alan Wood ,  Trung Doan

发明人： Alan Wood ,  Trung Doan

IPC分类号： H01L23/04

CPC分类号： H01L23/3114 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05172 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05184

摘要： A semiconductor component includes back side pin contacts fabricated using a circuit side fabrication method. The component also includes a thinned semiconductor die having a pattern of die contacts, and conductive members formed by filled openings in the die contacts and the die. In addition, the pin contacts are formed by terminal portions of the conductive members. The fabrication method includes the steps of forming the openings and the conductive members, and then thinning and etching the die to form the pin contacts. An alternate embodiment female component includes female conductive members configured to physically and electrically engage pin contacts on a mating component of a stacked assembly.

摘要翻译： 半导体部件包括使用电路侧制造方法制造的后侧引脚触点。 该部件还包括具有模接触图案的薄化半导体管芯，以及由管芯接触件和管芯中的填充开口形成的导电部件。 此外，引脚触点由导电构件的端子部分形成。 制造方法包括形成开口和导电构件的步骤，然后使模具变薄和蚀刻以形成引脚触点。 替代实施例的阴部件包括阴导电部件，其被配置为物理地和电接合堆叠组件的配合部件上的销触点。

公开(公告)号：US20050239265A1

公开(公告)日：2005-10-27

申请号：US11170452

申请日：2005-06-29

申请人： Trung Doan ,  Gurtej Sandhu

发明人： Trung Doan ,  Gurtej Sandhu

IPC分类号： H01L21/76 ,  H01L21/762

CPC分类号： H01L21/76224

摘要： In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOn and RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)x and (CH3)ySi(OH)4-y is formed to partially fill the trench. At least some of the Si(OH)x if present is converted to SiO2 and at least some of (CH3)ySi(OH)4-y if present is converted to (CH3)xSiO2-x. Next, a layer of an electrically insulative material is formed to fill the trench.

摘要翻译： 根据本发明的一个方面，形成沟槽隔离区域的方法包括在衬底内形成沟槽。 形成硅烷醇层以部分地填充沟槽，然后将至少一些硅烷醇转化成包括SiO 2和RSiO n N的至少一种的化合物，其中 R包括有机基团。 在转化的硅烷醇上形成电绝缘材料以填充沟槽。 在本发明的另一方面，形成沟槽隔离区域的方法包括在衬底内形成沟槽。 Si（OH）x和（CH 3）3 Si（OH）4-y中的至少一种的第一层 形成为部分地填充沟槽。 如果存在的话，至少有一些Si（OH）x X x被转化为SiO 2，并且至少一些（CH 3 3） 如果存在，则将Si（OH）4-y X转化为（CH 3 3）x SiO 2-x 。 接下来，形成电绝缘材料层以填充沟槽。

公开(公告)号：US20050173794A1

公开(公告)日：2005-08-11

申请号：US11109133

申请日：2005-04-05

申请人： Trung Doan

发明人： Trung Doan

IPC分类号： H01L23/495 ,  H01L23/522 ,  H01L23/48 ,  H01L21/76

CPC分类号： H01L24/06 ,  H01L23/4951 ,  H01L23/522 ,  H01L23/525 ,  H01L24/05 ,  H01L24/48 ,  H01L24/72 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/05552

摘要： An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternately, a connector may contact a portion of the conductive trace to make contact therewith.

摘要翻译： 一种用于将半导体管芯附接到引线框架的装置和方法，其中半导体管芯的电接触点通过多个导电迹线重新定位到半导体管芯的外围。 多个引线从引线框架延伸超过靠近半导体管芯外围的导电迹线，并且以LOC布置直接附接到导电迹线并与之形成电接触。 或者，连接器可以接触导电迹线的一部分以与其接触。