公开(公告)号：US11980046B2

公开(公告)日：2024-05-07

申请号：US16884375

申请日：2020-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yung-Chang Chang ,  Ming Chyi Liu

IPC: H10K50/818 ,  H10K50/828 ,  H10K59/122 ,  H10K59/124 ,  H10K59/12

CPC classification number: H10K50/818 ,  H10K50/828 ,  H10K59/122 ,  H10K59/124 ,  H10K59/12

Abstract: In some embodiments, the present disclosure relates to a display device that includes a first reflector electrode and a second reflector electrode that is separated from the first reflector electrode. The display device further includes an isolation structure that overlies the first and second reflector electrodes. The isolation structure includes a first and second portion. The first portion overlies the first reflector electrode and has a first thickness. The second portion overlies the second reflector electrode, has a second thickness greater than the first thickness, and is separated from the first portion of the isolation structure. The display device also includes a first optical emitter structure and a second optical emitter structure that respectively overlie the first portion and the second portion of the isolation structure.

公开(公告)号：US11749763B2

公开(公告)日：2023-09-05

申请号：US17148657

申请日：2021-01-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ming Chen ,  Lee-Chuan Tseng ,  Ming Chyi Liu ,  Po-Chun Liu

IPC: H01L31/0352 ,  H01L31/02 ,  H01L31/0216 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/105 ,  H01L31/18

CPC classification number: H01L31/035281 ,  H01L31/02005 ,  H01L31/028 ,  H01L31/02019 ,  H01L31/02161 ,  H01L31/0312 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1037 ,  H01L31/1808 ,  H01L31/1812 ,  Y02E10/547

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. An epitaxial pillar of SiGe or Ge extends upward from the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric layer is arranged over an upper surface of the substrate and is disposed around the lower epitaxial region to extend over outer edges of the well region. The dielectric layer has inner sidewalls that contact outer sidewalls of the epitaxial pillar. A dielectric sidewall structure has a bottom surface that rests on an upper surface of the dielectric layer and has inner sidewalls that extend continuously from the upper surface of the dielectric layer to a top surface of the epitaxial pillar.

公开(公告)号：US20220320160A1

公开(公告)日：2022-10-06

申请号：US17361785

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming Chyi Liu ,  Hung-Shu Huang

IPC: H01L27/146

Abstract: In some embodiments, the present disclosure relates to an image sensor, including a semiconductor substrate, a plurality of photodiodes disposed within the semiconductor substrate, and a deep trench isolation structure separating the plurality of photodiodes from one another and defining a plurality of pixel regions corresponding to the plurality of photodiodes. The plurality of pixel regions includes a first pixel region sensitive to a first region of a light spectrum, a second pixel region sensitive to a second region of the light spectrum, and a third pixel region sensitive to a third region of the light spectrum. The first pixel region is smaller than the second pixel region or the third pixel region.

公开(公告)号：US11437785B2

公开(公告)日：2022-09-06

申请号：US16579692

申请日：2019-09-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhih-Bin Chen ,  Ming Chyi Liu

IPC: H01S5/183 ,  H01S5/0239 ,  H01S5/02335 ,  H01S5/02

Abstract: A vertical cavity surface emitting laser (VCSEL) device includes a microlens arranged over a reflector stack. The reflector stack includes alternating reflector layers of a first material and a second material. The microlens stack includes a first lens layer, a second lens layer arranged over the first lens layer, and a third lens layer arranged over the second lens layer. The first lens layer includes a first average concentration of a first element and has a first width. The second lens layer includes a second average concentration of the first element greater than the first average concentration and has a second width smaller than the first width. The third lens layer includes a third average concentration of the first element greater than the second average concentration and has a third width smaller than the second width.

公开(公告)号：US11410999B2

公开(公告)日：2022-08-09

申请号：US16797334

申请日：2020-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Huan Chen ,  Chien-Chih Chou ,  Alexander Kalnitsky ,  Kong-Beng Thei ,  Ming Chyi Liu ,  Shih-Chung Hsiao ,  Jhih-Bin Chen

IPC: H01L27/092 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/51 ,  H01P1/15 ,  H01L23/48

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

公开(公告)号：US20220230939A1

公开(公告)日：2022-07-21

申请号：US17150048

申请日：2021-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Ling Shih ,  Ming Chyi Liu ,  Jiech-Fun Lu

IPC: H01L23/48 ,  H01L21/768 ,  H01L27/146

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) including a conductive structure disposed within a dielectric structure along a first side of a semiconductor substrate, an insulating structure disposed along inner sidewalls of the semiconductor substrate, the inner sidewalls of the semiconductor substrate extending through the semiconductor substrate, a blocking layer disposed along inner sidewalls of the insulating structure, and a through-substrate via (TSV) comprising a first portion and a second portion, the first portion extending from a second side of the semiconductor substrate to a horizontally-extending surface of the insulating structure that protrudes outward from the inner sidewalls of the insulating structure, the second portion extending from the first portion to the conductive structure and has a maximum width less than that of the first portion.

公开(公告)号：US11361971B2

公开(公告)日：2022-06-14

申请号：US17032362

申请日：2020-09-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hsing Chang ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L21/3065 ,  H01L21/308 ,  H01L49/02

Abstract: In some methods, a first recess is etched in a selected region of a substrate. A first polymer liner is formed on sidewalls and a bottom surface of the first recess. A portion of the first polymer liner is removed from the bottom surface, and a remaining portion of the first polymer liner is left along the sidewalls. The first recess is deepened to establish a second recess while the remaining portion of the first polymer liner is left along the sidewalls. A first oxide liner is formed along the sidewalls and along sidewalls and a bottom surface of the second recess. A portion of the first oxide liner is removed from a bottom surface of the second recess, while a remaining portion of the first oxide liner is left on the sidewalls of the first recess and the sidewalls of the second recess.

公开(公告)号：US11209673B2

公开(公告)日：2021-12-28

申请号：US16733488

申请日：2020-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shih-Wei Lin ,  Ming Chyi Liu

IPC: G02F1/01 ,  G02F1/225 ,  G02B6/12

Abstract: Various embodiments of the present disclosure are directed towards a modulator device including a first waveguide and a heater structure. An input terminal is configured to receive impingent light. The first waveguide has a first output region and a first input region coupled to the input terminal. A second waveguide is optically coupled to the first waveguide. The second waveguide has a second output region and a second input region coupled to the input terminal. An output terminal is configured to provide outgoing light that is modulated based on the impingent light. The output terminal is coupled to the first output region and the second output region. The heater structure overlies the first waveguide. A bottom surface of the heater structure is aligned with a bottom surface of the first waveguide. The first waveguide is spaced laterally between sidewalls of the heater structure.

公开(公告)号：US11171147B2

公开(公告)日：2021-11-09

申请号：US16359027

申请日：2019-03-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chieh Chen ,  Ming Chyi Liu ,  Shih-Chang Liu

IPC: H01L27/11517 ,  H01L27/11563

Abstract: Various embodiments provide a flash memory with an improved gate structure and a method of creating the same. The flash memory includes a plurality of memory cells that include a memory gate, a selection gate, a gate dielectric layer, and a protective cap formed on an upper surface of the gate dielectric layer. The protective cap protects the gate dielectric layer, and prevents the memory and selection gates from being unintentionally electrically connected to each other by conductive material.

公开(公告)号：US20210296451A1

公开(公告)日：2021-09-23

申请号：US16821247

申请日：2020-03-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kaochao Chen ,  Chia-Cheng Ho ,  Ming Chyi Liu

IPC: H01L29/40 ,  H01L21/768 ,  H01L29/16 ,  H01L29/78 ,  H01L29/06 ,  H01L21/3105

Abstract: An integrated chip includes a field plate overlying an isolation structure. A gate electrode overlies a substrate between a source region and a drain region. An etch stop layer laterally extends from an upper surface of the gate electrode to a front-side of the substrate. The etch stop layer overlies a drift region disposed between the source region and the drain region. The field plate is disposed within a first inter-level dielectric (ILD) layer overlying the substrate. The field plate extends from a top surface of the first ILD layer to an upper surface of the etch stop layer. The isolation structure is disposed within the substrate and extends from the front-side of the substrate to a point below the front-side of the substrate. The isolation structure is disposed laterally between the gate electrode and the drain region.