公开(公告)号：US06917457B2

公开(公告)日：2005-07-12

申请号：US10889027

申请日：2004-07-13

申请人： Nobuyuki Otsuka ,  Shigeo Yoshii ,  Masahiro Kitoh ,  Toshiya Yokogawa

发明人： Nobuyuki Otsuka ,  Shigeo Yoshii ,  Masahiro Kitoh ,  Toshiya Yokogawa

IPC分类号： G02F1/015 ,  G02F1/017

CPC分类号： B82Y20/00 ,  G02F1/015 ,  G02F1/017 ,  G02F2202/32 ,  G02F2203/02 ,  G02F2203/10

摘要： A vertical optical modulator comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type bonded to the first semiconductor layer; a third semiconductor layer of the second conductivity type; a dielectric layer formed between the second semiconductor layer and the third semiconductor layer; an antenna electrode having a plurality of conductive pieces which are formed within the dielectric layer so as to have a net-like shape as a whole, to be separated from one another at the intersections of the net-like shape, and to be in contact with both the second semiconductor layer and the third semiconductor layer; a first electrode electrically connected to the first semiconductor layer; and a second electrode electrically connected to the third semiconductor layer.

摘要翻译： 一种垂直光学调制器，包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层结合到第一半导体层; 第二导电类型的第三半导体层; 形成在所述第二半导体层和所述第三半导体层之间的电介质层; 具有多个导电片的天线电极，其形成在电介质层内以形成网状整体，在网状形状的交点处彼此分离并且接触 同时具有第二半导体层和第三半导体层; 电连接到第一半导体层的第一电极; 以及电连接到第三半导体层的第二电极。

公开(公告)号：US06855571B1

公开(公告)日：2005-02-15

申请号：US10366722

申请日：2003-02-14

申请人： Gaku Sugahara ,  Atsushi Yamada ,  Akihiko Ishibashi ,  Toshiya Yokogawa

发明人： Gaku Sugahara ,  Atsushi Yamada ,  Akihiko Ishibashi ,  Toshiya Yokogawa

IPC分类号： H01L21/00 ,  H01L21/20 ,  H01L33/00 ,  H01S5/02 ,  H01S5/22 ,  H01S5/223 ,  H01S5/343

CPC分类号： B82Y20/00 ,  H01L21/02378 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L33/005 ,  H01S5/0213 ,  H01S5/0655 ,  H01S5/2214 ,  H01S5/2231 ,  H01S5/34333 ,  H01S2304/00 ,  H01S2304/12

摘要： The present invention provides a method for fabricating a GaN-based semiconductor laser device comprising the steps of forming a GaN-based semiconductor layer 102 on a substrate 101; forming, on the surface of the first GaN-based semiconductor layer, a mask layer 103 that comprises a striped pattern composed of a plurality of band-like portions 103a that are regularly arranged in the width direction and an alignment pattern formed by altering the regularity of some portion of the plurality of band-like portions 103a; depositing a second GaN-based semiconductor layer 104 on the mask layer 103 by the selective lateral growth method with starting points at portions of the first GaN-based semiconductor layer 104 that are exposed from the mask layer 103; forming a multi-layered semiconductor that comprises an n-type GaN-based semiconductor layers 105 to 107, an active layer 108, and a p-type GaN-based semiconductor layers 109 to 111 on the second GaN-based semiconductor layer 104; and forming a current injection region 112 directly above the band-like portion 103a while using the alignment pattern as a reference to position the current injection region.

摘要翻译： 本发明提供一种制造GaN基半导体激光器件的方法，包括以下步骤：在衬底101上形成GaN基半导体层102; 在第一GaN基半导体层的表面上形成掩模层103，掩模层103包括由在宽度方向上规则排列的多个带状部分103a组成的条纹图案和通过改变规则性而形成的取向图案 多个带状部分103a的一些部分; 通过选择性横向生长方法在从掩模层103暴露的第一GaN基半导体层104的部分处的起始点，在掩模层103上沉积第二GaN基半导体层104; 形成包含在第二GaN基半导体层104上的n型GaN基半导体层105至107，有源层108和p型GaN基半导体层109至111的多层半导体; 并且在使用对准图案作为基准的同时，在带状部分103a的正上方形成电流注入区域112来定位电流注入区域。

公开(公告)号：US06690035B1

公开(公告)日：2004-02-10

申请号：US09980598

申请日：2001-11-01

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

IPC分类号： H01L310312

CPC分类号： H01L29/155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/365 ,  H01L29/812 ,  H01L29/872

摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.

摘要翻译： 有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。 由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。 在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值 通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。

公开(公告)号：US06674131B2

公开(公告)日：2004-01-06

申请号：US10069654

申请日：2002-02-26

申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Takeshi Uenoyama ,  Koji Miyazaki

发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Takeshi Uenoyama ,  Koji Miyazaki

IPC分类号： H01L29423

CPC分类号： H01L21/8213 ,  H01L21/8252 ,  H01L27/0629 ,  H01L27/0688 ,  H01L29/105 ,  H01L29/157 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/7725 ,  H01L29/7838 ,  H01L29/812 ,  H01L29/872 ,  Y10S438/931 ,  Y10S438/957

摘要： In a SiC substrate (10), a first active region (12) composed of n-type heavily doped layers (12a) and undoped layers (12b), which are alternately stacked, and a second active region (13) composed of p-type heavily doped layers (13a) and undoped layers (13b), which are alternately stacked, are provided upwardly in this order. A Schottky diode (20) and a pMOSFET (30) are provided on the first active region (12). An nMOSFET (40), a capacitor (50), and an inductor (60) are provided on the second active region (13). The Schottky diode (20) and the MOSFETs (30, 40) have a breakdown voltage characteristic and a carrier flow characteristic due to a multilayer structure composed of &dgr;-doped layers and undoped layers and are integrated in a common substrate.

摘要翻译： 在SiC衬底（10）中，交替堆叠由n型重掺杂层（12a）和未掺杂层（12b）组成的第一有源区（12）和由p-型衬底构成的第二有源区（13） 交替层叠的重掺杂层（13a）和未掺杂层（13b）按顺序向上设置。 肖特基二极管（20）和pMOSFET（30）设置在第一有源区（12）上。 在第二有源区域（13）上设置有nMOSFET（40），电容器（50）和电感器（60）。 肖特基二极管（20）和MOSFET（30,40）由于由δ掺杂层和​​未掺杂层组成的多层结构而具有击穿电压特性和载流子特性，并且集成在公共衬底中。

公开(公告)号：US06617653B1

公开(公告)日：2003-09-09

申请号：US10048344

申请日：2002-01-30

申请人： Toshiya Yokogawa ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Takeshi Uenoyama

发明人： Toshiya Yokogawa ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kunimasa Takahashi ,  Takeshi Uenoyama

IPC分类号： H01L2994

CPC分类号： H01L29/7813 ,  H01L21/0455 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7725 ,  H01L29/78 ,  H01L29/7828 ,  H01L29/7838

摘要： P-type active region 12; n-type source/drain regions 13a and 13b; gate insulating film 14 made of a thermal oxide film; gate electrode 15; source/drain electrodes 16a and 16b, are provided over a p-type SiC substrate 11. In the active region 12, p-type heavily doped layers 12a, which are thin enough to create a quantum effect, and thick undoped layers 12b are alternately stacked. When carriers flow, scattering of impurity ions in the active region is reduced, and the channel mobility increases. In the OFF state, a depletion layer expands throughout the active region, and the breakdown voltage increases. As a result of reduction in charges trapped in the gate insulating film or near the interface between the gate insulating film and the active region, the channel mobility further increases.

公开(公告)号：US06580125B2

公开(公告)日：2003-06-17

申请号：US10204097

申请日：2002-08-15

申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

IPC分类号： H01L2976

CPC分类号： H01L29/7395 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7828

摘要： A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.

摘要翻译： DMOS器件（或IGBT）包括SiC衬底2，形成在外延层中的n-SiC层3（漂移区），栅极绝缘膜6，栅电极7a，形成为围绕栅电极的源电极7b 如图7a所示，形成在SiC衬底2的下表面上的漏极电极7c，形成为从源电极7b的下边缘形成的p-SiC层4，n + SiC层3到栅电极7a的相关边缘 。 此外，该器件包括含有高浓度氮的n型掺杂层10a和未掺杂层10b，层叠在除了形成n + SiC层5的区域之外的外延层的表面部分的区域中 。 通过利用量子效应，器件可以使其导通电阻降低，并且当其处于截止状态时也可以使其击穿电压增加。

公开(公告)号：US06306211B1

公开(公告)日：2001-10-23

申请号：US09523671

申请日：2000-03-10

申请人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Masao Uchida ,  Toshiya Yokogawa

发明人： Kunimasa Takahashi ,  Makoto Kitabatake ,  Masao Uchida ,  Toshiya Yokogawa

IPC分类号： C30B2514

CPC分类号： H01L29/66068 ,  C30B25/02 ,  C30B25/14 ,  C30B29/52 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02433 ,  H01L21/02529 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02634 ,  H01L21/02658 ,  H01L21/0455 ,  H01L29/365 ,  H01L29/66431

摘要： In a chamber, a substrate is mounted on a susceptor and then heated to an elevated temperature. Source and diluting gases are supplied into the chamber through source and diluting gas supply pipes provided with respective flow meters. In addition, a doping gas is also supplied through an additive gas supply pipe, which is provided with a pulse valve, and a gas inlet pipe into the chamber by repeatedly opening and closing the pulse valve. In this manner, a doped layer is grown epitaxially on the substrate. In this case, a pulsed flow of the doping gas is directly supplied through the pulse valve onto the substrate from the outlet port of a pressure reducer for a doping gas cylinder. As a result, a steeply rising dopant concentration profile appears in a transition region between the substrate and the doped layer, and the surface of the doped layer is planarized.

摘要翻译： 在室中，将基底安装在基座上，然后加热到升高的温度。 源和稀释气体通过源和稀释供应有相应流量计的气体供应管道供应到室中。 此外，还通过反复打开和关闭脉冲阀，通过设置有脉冲阀的添加剂气体供给管和进入管中的气体导入管来供给掺杂气体。 以这种方式，在衬底上外延生长掺杂层。 在这种情况下，掺杂气体的脉冲流通过脉冲阀从用于掺杂气体筒的减压器的出口直接供给到基板上。 结果，在衬底和掺杂层之间的过渡区域中出现急剧上升的掺杂剂浓度分布，并且掺杂层的表面被平坦化。

公开(公告)号：US09252330B2

公开(公告)日：2016-02-02

申请号：US13813792

申请日：2011-08-05

申请人： Akihiro Isozaki ,  Akira Inoue ,  Atsushi Yamada ,  Toshiya Yokogawa

发明人： Akihiro Isozaki ,  Akira Inoue ,  Atsushi Yamada ,  Toshiya Yokogawa

IPC分类号： H01L33/32 ,  H01L33/16 ,  H01L33/20 ,  H01L33/00

CPC分类号： H01L33/32 ,  H01L33/0079 ,  H01L33/16 ,  H01L33/20 ,  H01L2933/0083

摘要： A semiconductor light-emitting element according to the present invention includes: an n-type nitride semiconductor layer 21; a p-type nitride semiconductor layer 23; an active layer region 22 which includes an m plane nitride semiconductor layer and which is interposed between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer; an n-type electrode 30 which is electrically connected to the n-type nitride semiconductor layer; a p-type electrode 40 which is electrically connected to the p-type nitride semiconductor layer; a light-emitting face, through which polarized light that has been produced in the active layer region is extracted out of this element; and a striped structure 50 which is provided for the light-emitting face and which has a plurality of projections that run substantially parallel to the a-axis direction of the m plane nitride semiconductor layer.

摘要翻译： 根据本发明的半导体发光元件包括：n型氮化物半导体层21; p型氮化物半导体层23; 包括m面氮化物半导体层并且介于n型氮化物半导体层和p型氮化物半导体层之间的有源层区域22; 与n型氮化物半导体层电连接的n型电极30; 与p型氮化物半导体层电连接的p型电极40; 从该元件中提取出在有源层区域中产生的偏振光的发光面; 以及条形结构50，其被设置用于发光面，并且具有大致平行于m面氮化物半导体层的a轴方向延伸的多个突起。

公开(公告)号：US08823026B2

公开(公告)日：2014-09-02

申请号：US13880027

申请日：2012-05-02

申请人： Toshiya Yokogawa ,  Junko Iwanaga ,  Akira Inoue

发明人： Toshiya Yokogawa ,  Junko Iwanaga ,  Akira Inoue

IPC分类号： H01L33/00 ,  H01L33/32 ,  H01L33/02 ,  H01L33/16

CPC分类号： H01L33/32 ,  H01L33/02 ,  H01L33/16

摘要： A nitride-based semiconductor light-emitting device of an embodiment includes a semiconductor multilayer structure having a growing plane which is an m-plane and being made of a GaN-based semiconductor. The semiconductor multilayer structure includes a n-type semiconductor layer, a p-type semiconductor layer, a p-side electrode provided on the p-type semiconductor layer, and an active layer interposed between the n-type semiconductor layer and the p-type semiconductor layer. The ratio of the thickness of the active layer to the thickness of the n-type semiconductor layer, D, is in the range of 1.8×10−4≦D≦14.1×10−4. The area of the p-side electrode, S, is in the range of 1×102 μm2≦S≦9×104 μm2. A maximum current density which leads to 88% of a maximum of the external quantum efficiency is not less than 2 A/mm2.

摘要翻译： 实施方式的氮化物系半导体发光元件具有半导体层叠结构，该半导体层叠结构具有作为m面的生长面并由GaN系半导体构成。 半导体多层结构包括n型半导体层，p型半导体层，设置在p型半导体层上的p侧电极以及介于n型半导体层和p型半导体层之间的有源层 半导体层。 有源层的厚度与n型半导体层的厚度D的比值在1.8×10-4＆lt; 1lE; D＆nlE; 14.1×10-4的范围内。 p侧电极S的面积在1×102μm2＆amp; NlE; S＆NlE; 9×104μm2的范围内。 导致外部量子效率最大值的88％的最大电流密度不小于2A / mm2。

公开(公告)号：US08748899B2

公开(公告)日：2014-06-10

申请号：US13447368

申请日：2012-04-16

申请人： Toshiya Yokogawa ,  Mitsuaki Oya ,  Atsushi Yamada ,  Ryou Kato

发明人： Toshiya Yokogawa ,  Mitsuaki Oya ,  Atsushi Yamada ,  Ryou Kato

IPC分类号： H01L29/778 ,  H01L33/32 ,  H01L29/78

CPC分类号： H01L33/32 ,  H01L33/16 ,  H01L33/40 ,  H01L2224/14 ,  H01L2224/16225 ,  H01L2924/181 ,  Y10T436/112499 ,  H01L2924/00012

摘要： A nitride-based semiconductor device according to the present disclosure includes a nitride-based semiconductor multilayer structure 20 with a p-type semiconductor region, of which the surface 12 defines a tilt angle of one to five degrees with respect to an m plane, and an electrode 30, which is arranged on the p-type semiconductor region. The p-type semiconductor region is made of an AlxInyGazN (where x+y+z=1, x≧0, y≧0 and z≧0) semiconductor layer 26. The electrode 30 includes an Mg layer 32, which is in contact with the surface 12 of the p-type semiconductor region, and a metal layer 34 formed on the Mg layer 32. The metal layer 34 is formed from at least one metallic element that is selected from the group consisting of Pt, Mo and Pd.

摘要翻译： 根据本公开的氮化物基半导体器件包括具有p型半导体区域的氮化物基半导体多层结构20，其表面12相对于m平面限定1至5度的倾斜角，以及 布置在p型半导体区域上的电极30。 p型半导体区域由Al x In y Ga z N（其中x + y + z = 1，x≥0，y≥0和z≥0）半导体层26制成。电极30包括Mg层32，其接触 与p型半导体区域的表面12以及形成在Mg层32上的金属层34.金属层34由选自Pt，Mo和Pd中的至少一种金属元素形成。