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公开(公告)号：US09885949B2
公开(公告)日：2018-02-06
申请号：US15207187
申请日：2016-07-11
发明人： Julien Mailfert , Werner Gillijns
CPC分类号： G03F1/36 , G03F1/70 , G06F17/5081
摘要： The disclosure is directed to a method for designing a lithographic mask to print a pattern of structural features, wherein an OPC-based methodology may be used for producing one or more simulated patterns as they would be printed through the optimized mask. A real mask is then produced according to the optimized design, and an actual print is made through the mask. To evaluate the printed pattern and the PW on wafer more accurately, experimental contours are extracted from the CD-SEM measurements of the printed pattern. The verification of the mask is based on a comparison between on the one hand the contour obtained from the printed pattern, and on the other hand the intended pattern and/or the simulated contour. A direct comparison can be made between simulation and experiment, without losing all the pieces of info contained in each single CD-SEM picture.
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公开(公告)号：US20180031981A1
公开(公告)日：2018-02-01
申请号：US15546592
申请日：2016-01-20
CPC分类号： G03F7/7065 , G03F1/60 , G03F1/84 , G03F7/705 , G03F7/70525 , G03F7/70641 , G03F7/70666 , G06F17/5009 , G06F17/5081 , G06F2217/12 , G06N20/00
摘要： A defect prediction method for a device manufacturing process involving processing one or more patterns onto a substrate, the method including: determining values of one or more processing parameters under which the one or more patterns are processed; and determining or predicting, using the values of the one or more processing parameters, an existence, a probability of existence, a characteristic, and/or a combination selected from the foregoing, of a defect resulting from production of the one or more patterns with the device manufacturing process.
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公开(公告)号：US20180018421A1
公开(公告)日：2018-01-18
申请号：US15207898
申请日：2016-07-12
发明人： Naiju K. Abdul , Adil Bhanji , Hemlata Gupta , Kerim Kalafala , Alex Rubin , Manish Verma
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5081 , G06F2217/62 , G06F2217/84
摘要： A method, system and computer program product perform timing analysis of an integrated circuit design with callback-based constraint processing for clock domain independence. A timing graph representation of the integrated circuit design includes nodes interconnected by edges. Loading timing abstracts representing the nodes of the timing graph precedes obtaining a timing result based on propagating timing values and associated timing tags from an input to an output of the integrated circuit design and processing timing constraints at one or more of the nodes as callbacks. Each timing tag indicates a clock domain. After applying a design change, one or more modified timing tags that are added or changed as a result of the design change are determined. The timing constraints associated with the modified timing tags are processed as callbacks, and the timing result are re-computed.
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公开(公告)号：US20180018420A1
公开(公告)日：2018-01-18
申请号：US15210109
申请日：2016-07-14
申请人： ARM Limited
IPC分类号： G06F17/50 , H01L21/768 , H01L23/528
CPC分类号： G06F17/5072 , G03F1/00 , G03F7/2022 , G06F17/5045 , G06F17/5081 , G06F19/00 , G06F2217/12 , G21K5/00 , H01L21/76892 , H01L23/528
摘要： A method for modifying metal portions of a layout data file associated with a self-aligned multiple patterning (SAMP) process. The method comprises receiving the layout data file that includes one or more active metal portions and layout information associated with an integrated circuit. The method also comprises converting the layout data file to further include mask information having at least a first set of trim features associated with one or more redundant metal portions and one or more active metal portions of the layout data file. The method also comprises determining the one or more redundant metal portions to be perforated. The method further comprises modifying the mask information to further include a second set of trim features for perforating the one or more redundant metal portions. The first set of trim features and the second set of trim features are associated with a trim mask of the SAMP process.
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公开(公告)号：US20180018410A1
公开(公告)日：2018-01-18
申请号：US15210052
申请日：2016-07-14
发明人： YU-JEN CHANG , KUO-NAN YANG , JUI-JUNG HSU , CHIH-HUNG WU , CHUNG-HSING WANG
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/82 , G06F2217/84
摘要： An integrated circuit (IC) design method is disclosed. The method includes: using a computer to perform synthesis upon a register transfer level (RTL) IC design to generate a gate level netlist; performing place and route (P&R) upon the gate level netlist to generate a layout; determining a sink current distribution information of the layout; and generating a voltage (IR) drop/electro-migration (EM) analysis result of the layout according to the sink current distribution information; wherein the layout includes a cell having a cell height that is N times higher than a single cell height, where N is an integer and greater than 1, and the cell corresponds to N power/ground (P/G) rail sets; wherein the sink current distribution information includes a proportion of a sink current flowing through each of the N power/ground (P/G) rail sets with respect to the cell when operated. Associated non-transitory computer-readable medium is also disclosed.
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公开(公告)号：US20180011962A1
公开(公告)日：2018-01-11
申请号：US15203954
申请日：2016-07-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/504 , G06F2217/12 , G06F2217/14
摘要： A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.
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公开(公告)号：US09865486B2
公开(公告)日：2018-01-09
申请号：US15083692
申请日：2016-03-29
申请人： GLOBALFOUNDRIES INC.
发明人： Igor Arsovski , Jeanne P. Bickford , Mark W. Kuemerle , Susan K. Lichtensteiger , Jeanne H. Raymond
CPC分类号： H01L21/67271 , G01R31/2882 , G01R31/3004 , G01R31/31718 , G06F17/5036 , G06F17/5081 , G06F2217/10 , G06F2217/78 , G06F2217/84 , H01L21/67253 , H01L22/14
摘要： Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax. The chips are sorted into different process windows, based on the voltage identified.
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98.发明申请公开(公告)号：US20180004886A1
公开(公告)日：2018-01-04
申请号：US15471146
申请日：2017-03-28
发明人： Prasenjit RAY , Lee-Chung LU , Meng-Kai HSU , Wen-Hao CHEN , Yuan-Te HOU
IPC分类号： G06F17/50
CPC分类号： G06F17/5077 , G06F17/5068 , G06F17/5081 , H01L23/52 , H01L27/027
摘要： A method is applied to reconfigure a set of uncrowned standard cells in a layout of a semiconductor apparatus. Each uncrowned standard cell includes a standard first array. Each standard first array includes a first stacked arrangement of vias interspersed with first segments of corresponding M(i)˜M(N) metallization layers. The M(N) metallization layer includes second segments which connect corresponding first segments of the M(N) metallization layer in the first standard arrays. The method includes crowning each first standard array in the set with a corresponding second standard array. Each standard second array includes a second stacked arrangement of vias interspersed with corresponding first segments of corresponding M(N+1)˜M(N+Q) metallization layers. The method further includes: adding, to the M(N+Q) layer, second segments which connect corresponding first segments of the M(N+Q) metallization layer in the corresponding second standard arrays.
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公开(公告)号：US09858383B2
公开(公告)日：2018-01-02
申请号：US14973893
申请日：2015-12-18
发明人： Kerim Kalafala , Tsz-Mei Ko , Ravichander Ledalla , Alice H. Lee , Adam P. Matheny , Jose L. Neves , Gregory M. Schaeffer
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5036 , G06F2217/78 , G06F2217/82 , G06F2217/84
摘要： An incremental parasitic extraction system includes a noise analysis module configured to perform a first noise analysis on at least one first net with respect to at least one aggressor net. The incremental parasitic extraction system further includes an optimizer module and an extraction module. The optimizer module performs a first optimization activity on the at least one first net based on results of the first noise analysis. The optimizer module further generates a first invalidation list based on the first optimization activity, and a second invalidation list based on a type of the first optimization action so as to add the second invalidation list to the first invalidation list. The extraction module processes the first and second invalidation lists and performs an extraction and noise analysis process on the first and second invalidation lists so as to determine at least one new RC network and associated noise analysis results.
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公开(公告)号：US09858381B2
公开(公告)日：2018-01-02
申请号：US14928952
申请日：2015-10-30
发明人： Gaurav Malhotra
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5063 , G06F2217/10 , G06F2217/82
摘要： A method for manufacturing a serial link including a channel and a receiver, the link including linear time-invariant elements, the receiver including a continuous-time linear equalizer (CTLE) including a nonlinear block, and a slicer having an input. The method includes: for each of a plurality of candidate CTLE configurations: calculating a first probability density function (PDF), corresponding to a first signal value, at the input of the nonlinear block, calculating a first PDF, corresponding to the first signal value, at the output of the nonlinear block; calculating a second PDF, corresponding to a second signal value, at the input of the nonlinear block, calculating a second PDF, corresponding to the second signal value, at the output of the nonlinear block; and calculating a bit error rate.
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