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91.发明公开公开(公告)号：US20230387060A1
公开(公告)日：2023-11-30
申请号：US18195090
申请日：2023-05-09
IPC分类号： H01L23/00
CPC分类号： H01L24/20 , H01L24/19 , H01L2224/21 , H01L2224/19
摘要： An electronic assembly may include a component comprising conductive studs disposed over an active layer of the component. A first encapsulant layer may be disposed around four side surfaces of the component, over the active layer of the component, and contacting at least a portion of the sides of the conductive studs. A substantially planar surface may be disposed over the active layer of the component, wherein the substantially planar surface comprises ends of the conductive studs and the first encapsulant layer. The first encapsulant layer comprises a roughness less than 500 nanometers. First conductive elements may be disposed over the encapsulant and coupled with the conductive studs. A second layer of encapsulant may be disposed over the first conductive elements.
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92.发明公开公开(公告)号：US20230387035A1
公开(公告)日：2023-11-30
申请号：US18232713
申请日：2023-08-10
发明人： Kam-Tou SIO , Cheng-Chi Chuang , Chia-Tien Wu , Jiann-Tyng Tzeng , Shih-Wei Peng , Wei-Cheng Lin
IPC分类号： H01L23/538 , H01L23/00 , H01L21/48
CPC分类号： H01L23/5389 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/19 , H01L21/4853 , H01L21/486 , H01L21/4857 , H01L24/20 , H01L2224/214
摘要： The present disclosure describes a semiconductor structure having a power distribution network including first and second conductive lines. A substrate includes a first surface that is in contact with the power distribution network. A plurality of backside vias are in the substrate and electrically coupled to the first conductive line. A via rail is on a second surface of the substrate that opposes the first surface. A first interlayer dielectric is on the via rail and on the substrate. A second interlayer dielectric is on the first interlayer dielectric. A third interlayer dielectric is on the second interlayer dielectric. First and top interconnect layers are in the second and third interlayer dielectrics, respectively. Deep vias are in the interlayer dielectric and electrically coupled to the via rail. The deep vias are also connected to the first and top interconnect layers. A power supply in/out layer is on the third interlayer dielectric and in contact with the top interconnect layer.
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公开(公告)号：US20230384684A1
公开(公告)日：2023-11-30
申请号：US18358904
申请日：2023-07-25
发明人： Hung-Jui Kuo , Hui-Jung Tsai , Tai-Min Chang
IPC分类号： G03F7/42 , H01L23/538 , H01L23/00 , H01L21/683 , H01L21/48 , H01L21/56 , H01L23/31
CPC分类号： G03F7/426 , H01L23/5383 , H01L23/5386 , H01L23/5389 , H01L24/20 , H01L24/19 , H01L21/6835 , H01L21/4853 , H01L21/4857 , H01L21/4864 , H01L21/565 , H01L21/568 , H01L23/3128 , H01L2224/214 , H01L2221/68372
摘要： A method for removing a resist layer including the following steps is provided. A patterned resist layer on a material layer is formed. A stripping solution is applied to the patterned resist layer to dissolve the patterned resist layer without dissolving the material layer, wherein the stripping solution comprises a non-dimethyl sulfoxide solvent and an alkaline compound, the non-dimethyl sulfoxide solvent comprises an aprotic solvent and a protic solvent.
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公开(公告)号：US20230378116A1
公开(公告)日：2023-11-23
申请号：US18362730
申请日：2023-07-31
发明人： Cheng-Yuan Li , Kuo-Cheng Lee , Yun-Wei Cheng , Yen-Liang Lin
IPC分类号： H01L23/00
CPC分类号： H01L24/20 , H01L24/24 , H01L24/82 , H01L2224/82896 , H01L2224/24145 , H01L2224/8212 , H01L2224/2105
摘要： Redistribution layers of integrated circuits include one or more arrays of conductive contacts that are configured and arranged to allow a bonding wave to displace air between the redistribution layers during bonding. This configuration and arrangement of the one or more arrays minimize discontinuities, such as pockets of air to provide an example, between the redistribution layers during the bonding.
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公开(公告)号：US20230378075A1
公开(公告)日：2023-11-23
申请号：US18230829
申请日：2023-08-07
发明人： Chen-Hua Yu , Chung-Shi Liu , Chih-Wei Lin , Ming-Da Cheng
IPC分类号： H01L23/538 , H01L21/56 , H01L23/498 , H01L23/31 , H01L25/10 , H01L23/00
CPC分类号： H01L23/5384 , H01L21/56 , H01L23/49827 , H01L23/49805 , H01L23/49838 , H01L23/5386 , H01L23/3128 , H01L25/105 , H01L24/19 , H01L24/20 , H01L24/73 , H01L24/92 , H01L24/83 , H01L2924/1533 , H01L21/568 , H01L2224/04105 , H01L2224/12105 , H01L2224/32225 , H01L2224/73267 , H01L2225/1035 , H01L2225/1058 , H01L2924/15311 , H01L2924/143 , H01L2924/141 , H01L2224/92244 , H01L2924/1431 , H01L2924/1432 , H01L2924/1434 , H01L2924/1436 , H01L2924/1437 , H01L23/49816 , H01L23/5389 , H01L2224/19 , H01L2224/2101 , H01L2224/27334 , H01L2224/214 , H01L24/32 , H01L2021/6006
摘要： A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.
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公开(公告)号：US11824033B2
公开(公告)日：2023-11-21
申请号：US18149342
申请日：2023-01-03
发明人： Gyoyoung Jung , Jinsu Kim , Hyunsuk Yang , Kiju Lee , Hoyeon Jo , Ikkyu Jin
CPC分类号： H01L24/20 , H01L24/13 , H01L24/19 , H01L24/24 , H01L24/25 , H01L24/73 , H01L25/16 , H01L2224/13005 , H01L2224/13024 , H01L2224/2105 , H01L2224/2201 , H01L2224/2205 , H01L2224/24155 , H01L2224/24265 , H01L2224/2518 , H01L2224/25171 , H01L2224/73217 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1441 , H01L2924/1443 , H01L2924/19041 , H01L2924/19104
摘要： A semiconductor package including a core substrate, a semiconductor chip in the core substrate and having chip pads, a redistribution wiring layer covering a lower surface of the core substrate and including redistribution wirings electrically connected to the chip pads and a pair of capacitor pads exposed from an outer surface of the redistribution wiring layer, conductive pastes on the capacitor pads, respectively, and a capacitor via the conductive pastes and having first and second outer electrodes on the capacitor pads, respectively, may be provided. Each of the capacitor pads includes a pad pattern exposed from the outer surface of the redistribution wiring layer, and at least one via pattern at a lower portion of the pad pattern and electrically connected to at least one of the redistribution wirings. The via pattern is eccentric by a distance from a center line of the pad pattern.
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公开(公告)号：US11824032B2
公开(公告)日：2023-11-21
申请号：US17205669
申请日：2021-03-18
发明人： Wei-Yu Chen , Chi-Yang Yu , Kuan-Lin Ho , Chin-Liang Chen , Yu-Min Liang , Jiun Yi Wu
IPC分类号： H01L23/00 , H01L23/31 , H01L25/065 , H01L21/56
CPC分类号： H01L24/20 , H01L21/561 , H01L21/563 , H01L23/3185 , H01L23/3192 , H01L24/16 , H01L24/19 , H01L24/24 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/92 , H01L25/0652 , H01L25/0655 , H01L25/0657 , H01L24/14 , H01L2224/13 , H01L2224/13024 , H01L2224/14131 , H01L2224/16145 , H01L2224/16227 , H01L2224/19 , H01L2224/2101 , H01L2224/221 , H01L2224/24137 , H01L2224/32225 , H01L2224/73204 , H01L2224/73209 , H01L2224/73217 , H01L2224/81815 , H01L2224/92125 , H01L2225/06513 , H01L2225/06517 , H01L2924/1431 , H01L2924/1437
摘要： A chip package structure includes a fan-out package containing at least one semiconductor die, an epoxy molding compound (EMC) die frame laterally surrounding the at least one semiconductor die, and a redistribution structure. The fan-out package has chamfer regions at which horizontal surfaces and vertical surfaces of the fan-out package are connected via angled surfaces that are not horizontal and not vertical. The chip package structure may include a package substrate that is attached to the fan-out package via an array of solder material portions, and an underfill material portion that laterally surrounds the array of solder material portions and contacts an entirety of the angled surfaces. The angled surfaces eliminate a sharp corner at which mechanical stress may be concentrated, and distribute local mechanical stress in the chamfer regions over a wide region to prevent cracks in the underfill material portion.
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98.发明授权公开(公告)号：US11824031B2
公开(公告)日：2023-11-21
申请号：US16898064
申请日：2020-06-10
发明人： Chih-Cheng Lee , Jiming Li
CPC分类号： H01L24/20 , H01L23/3171 , H01L23/481 , H01L2924/15153
摘要： A semiconductor package structure and a method for manufacturing the same are provided. The semiconductor package structure includes a substrate, a chip and a dielectric structure. The substrate includes a first portion and a second portion surrounding the first portion. The second portion defines a cavity over the first portion. The chip includes a terminal on an upper surface of the chip. The dielectric structure fills the cavity and laterally encroaches over the upper surface of the chip. The dielectric structure is free from overlapping with the terminal of the chip.
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99.发明公开公开(公告)号：US20230369294A1
公开(公告)日：2023-11-16
申请号：US18360734
申请日：2023-07-27
发明人： Jen-Yuan CHANG , Chia-Ping LAI
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L21/56
CPC分类号： H01L25/0657 , H01L24/20 , H01L24/13 , H01L25/50 , H01L21/565 , H01L21/561 , H01L24/19 , H01L24/96 , H01L24/11 , H01L24/16 , H01L24/81 , H01L25/0652 , H01L2224/16146 , H01L2224/211 , H01L2224/13025 , H01L2924/1437
摘要： An array of complementary die sets is attached to a carrier substrate. A continuous complementary-level molding compound layer is formed around the array of complementary die sets. An array of primary semiconductor dies is attached to the array of complementary die sets. A continuous primary-level molding compound layer is formed around the array of primary semiconductor dies. The bonded assembly is diced by cutting along directions that are parallel to edges of the primary semiconductor dies. The sidewalls of the complementary dies are azimuthally tilted relative to sidewalls of the primary semiconductor dies, or major crystallographic directions of a single crystalline material in the carrier substrate are azimuthally tilted relative to sidewalls of the primary semiconductor dies.
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公开(公告)号：US20230361080A1
公开(公告)日：2023-11-09
申请号：US18352595
申请日：2023-07-14
发明人： Chia-Kuei Hsu , Ming-Chih Yew , Shu-Shen Yeh , Che-Chia Yang , Po-Yao Lin , Shin-Puu Jeng
IPC分类号： H01L25/065 , H01L21/48 , H01L21/56 , H01L23/31 , H01L23/538 , H01L23/00 , H01L23/48
CPC分类号： H01L25/0655 , H01L21/4857 , H01L21/561 , H01L23/3185 , H01L23/5383 , H01L23/5386 , H01L24/20 , H01L23/481 , H01L23/3128
摘要： An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.
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