公开(公告)号：US09412859B2

公开(公告)日：2016-08-09

申请号：US13792730

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract translation: 提供了形成半导体器件的方法。 在一个实施例中，提供了一种在栅极绝缘层上形成栅极绝缘层和栅电极结构的栅极结构。 所述方法提供了沿着平行于连接源极和漏极的方向延伸的方向，相对于栅极绝缘层减小栅电极结构的尺寸。 提供一种具有栅极结构的半导体器件结构，该栅极结构包括形成在栅极绝缘层上方的栅极绝缘层和栅电极结构，其中栅电极结构的尺寸沿着基本上平行于源极方向的方向延伸 漏极相对于栅极绝缘层的尺寸减小。 根据一些示例，提供具有栅极硅长度的栅极结构，其与由栅极结构引起的沟道宽度解耦。

公开(公告)号：US09373720B2

公开(公告)日：2016-06-21

申请号：US14052977

申请日：2013-10-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: The present invention relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and/or drain of the first transistor is at least partially separated from, respectively, the source and/or drain of the second transistor. The invention further relates to a process for realizing such a semiconductor structure.

Abstract translation: 本发明涉及包括至少第一和第二三维晶体管的半导体结构，其中第一晶体管和第二晶体管彼此并联电连接，并且其中每个晶体管包括源极和漏极，其中 第一晶体管的源极和/或漏极分别与第二晶体管的源极和/或漏极部分地分开。 本发明还涉及一种用于实现这种半导体结构的方法。

公开(公告)号：US09373509B2

公开(公告)日：2016-06-21

申请号：US14477358

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Peter Javorka ,  Jan Hoentschel

IPC: H01L21/30 ,  C23C14/48 ,  H01L21/336 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/266 ,  H01L21/3065 ,  H01J37/32

CPC classification number: H01L21/26586 ,  H01J37/32412 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/3065 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/7851

Abstract: A method to implant dopants onto fin-type field-effect-transistor (FINFET) fin surfaces with uniform concentration and depth levels of the dopants and the resulting device are disclosed. Embodiments include a method for pulsing a dopant perpendicular to an upper surface of a substrate, forming an implantation beam pulse; applying an electric or a magnetic field to the implantation beam pulse to effectuate a curvilinear trajectory path of the implantation beam pulse; and implanting the dopant onto a sidewall surface of a target FINFET fin on the upper surface of the substrate via the curvilinear trajectory path of the implantation beam pulse.

Abstract translation: 公开了将掺杂剂注入到具有均匀的掺杂剂和所得器件的浓度和深度水平的鳍式场效应晶体管（FINFET）鳍表面上的方法。 实施例包括用于脉冲掺杂物垂直于衬底的上表面的方法，形成注入束脉冲; 对注入束脉冲施加电场或磁场，以实现注入束脉冲的曲线轨迹路径; 以及通过所述注入束脉冲的曲线轨迹路径将所述掺杂剂注入到所述衬底的上表面上的靶FINFET鳍的侧壁表面上。

公开(公告)号：US09368513B2

公开(公告)日：2016-06-14

申请号：US14934369

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.

Abstract translation: 半导体器件包括位于衬底上方的半导体材料和位于半导体材料表面之上的栅极结构，该栅极结构覆盖该表面的非平面表面部分。 侧壁间隔物定位成与栅极结构相邻，并且包括具有N型和P型导电体之一的第一掺杂剂，其中侧壁间隔物覆盖栅极结构的整个侧壁表面并且部分覆盖半导体材料的表面 。 包括第一掺杂剂的源极/漏极延伸区域位于非平面表面部分内并且与侧壁间隔物对准，其中邻近非平坦表面部分的侧壁间隔部分内的第一掺杂剂的浓度基本对应于 到靠近非平面表面部分的源极/漏极延伸区域内的第一掺杂剂的浓度。

公开(公告)号：US20160163815A1

公开(公告)日：2016-06-09

申请号：US14693978

申请日：2015-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/66 ,  H01L29/45 ,  H01L29/06 ,  H01L21/283 ,  H01L29/78

CPC classification number: H01L29/665 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/45 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: The present disclosure provides in one aspect for a semiconductor device structure which may be formed by providing source/drain regions within a semiconductor substrate in alignment with a gate structure formed over the semiconductor substrate, wherein the gate structure has a gate electrode structure, a first sidewall spacer and a second sidewall spacer, the first sidewall spacer covering sidewall surfaces of the gate electrode structure and the sidewall spacer being formed on the first sidewall spacer. Furthermore, forming the semiconductor device structure may include removing the second sidewall spacer so as to expose the first sidewall spacer, forming a third sidewall spacer on a portion of the first sidewall spacer such that the first sidewall spacer is partially exposed, and forming silicide regions in alignment with the third sidewall spacer in the source/drain regions.

Abstract translation: 本公开在一个方面中提供了半导体器件结构，其可以通过在半导体衬底内提供与在半导体衬底上形成的栅极结构对准的源极/漏极区域形成，其中栅极结构具有栅电极结构，第一 侧壁间隔件和第二侧壁间隔件，所述第一侧壁间隔物覆盖所述栅极电极结构和所述侧壁间隔物的侧壁表面，所述侧壁间隔件形成在所述第一侧壁间隔物上。 此外，形成半导体器件结构可以包括去除第二侧壁间隔物以暴露第一侧壁间隔物，在第一侧壁间隔物的一部分上形成第三侧壁间隔物，使得第一侧壁间隔物部分地暴露，并且形成硅化物区域 与源极/漏极区域中的第三侧壁间隔物对准。

公开(公告)号：US09349734B2

公开(公告)日：2016-05-24

申请号：US14475720

申请日：2014-09-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Gerd Zschätzsch

IPC: H01L21/336 ,  H01L27/092 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/308 ,  H01L21/311 ,  H01L27/06

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28097 ,  H01L21/3083 ,  H01L21/8238 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/267 ,  H01L29/4941 ,  H01L29/4975 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

Abstract: The present disclosure provides a method of forming a semiconductor device structure with selectively fabricating semiconductor device structures having fully silicided (FuSi) gates and partially silicided gates. In aspects of the present disclosure, a semiconductor device structure with a first semiconductor device and a second semiconductor device is provided, wherein each of the first and second semiconductor devices includes a gate structure over an active region, each of the gate structures having a gate electrode material and a gate dielectric material. The gate electrode material of the first semiconductor device is recessed, resulting in a recessed first gate electrode material which is fully silicided during a subsequent silicidation process. On the gate electrode material of the second semiconductor device, a silicide portion is formed during the silicidation process.

Abstract translation: 本公开提供了一种形成半导体器件结构的方法，其选择性地制造具有完全硅化（FuSi）栅极和部分硅化栅极的半导体器件结构。 在本公开的方面中，提供了具有第一半导体器件和第二半导体器件的半导体器件结构，其中第一和第二半导体器件中的每一个在有源区域上包括栅极结构，每个栅极结构具有栅极 电极材料和栅极电介质材料。 第一半导体器件的栅电极材料凹陷，导致凹陷的第一栅电极材料，其在随后的硅化工艺期间被完全硅化。 在第二半导体器件的栅极电极材料上，在硅化处理期间形成硅化物部分。

公开(公告)号：US20160141393A1

公开(公告)日：2016-05-19

申请号：US15003370

申请日：2016-01-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Andreas Kurz ,  Sven Beyer ,  Wolfgang Buchholtz

IPC: H01L29/66 ,  H01L21/308 ,  H01L49/02 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/308 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L27/0738 ,  H01L28/20 ,  H01L29/66545

Abstract: A method includes forming a plurality of fins in a semiconductor substrate using a common patterning process. A conductive layer is formed above the plurality of fins. A mask is formed above the conductive layer. The conductive layer is etched using the mask to define trenches in the conductive layer. A first insulating layer is formed above the conductive layer and in the trenches. First and second contacts are formed connected to respective ends of the conductive layer.

Abstract translation: 一种方法包括使用共同的图案化工艺在半导体衬底中形成多个翅片。 在多个翅片上方形成导电层。 在导电层上方形成掩模。 使用掩模蚀刻导电层以在导电层中限定沟槽。 第一绝缘层形成在导电层上方和沟槽中。 第一和第二触点形成为连接到导电层的相应末端。

公开(公告)号：US20160071947A1

公开(公告)日：2016-03-10

申请号：US14482839

申请日：2014-09-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Maciej Wiatr ,  Stefan Flachowsky

IPC: H01L29/51 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/516 ,  H01L21/28194 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method disclosed herein includes providing a substrate including a semiconductor material. A first area of the substrate is recessed relative to a second area of the substrate, and an active region of a first transistor is formed in the recessed area. An active region of a second transistor is formed in the second area of the substrate. First and second dummy gate structures are formed over the active regions of the first transistor and the second transistor, respectively. At least a portion of the first and second dummy gate structures is replaced with at least a portion of a gate structure of the first transistor and the second transistor, respectively. The gate structure of the first transistor includes a ferroelectric material, and the gate structure of the second transistor does not include a ferroelectric material.

Abstract translation: 本文公开的方法包括提供包括半导体材料的衬底。 衬底的第一区域相对于衬底的第二区域凹陷，并且在凹陷区域中形成第一晶体管的有源区。 第二晶体管的有源区形成在衬底的第二区域中。 第一和第二伪栅极结构分别形成在第一晶体管和第二晶体管的有源区上。 第一和第二伪栅极结构的至少一部分分别由第一晶体管和第二晶体管的栅极结构的至少一部分替代。 第一晶体管的栅极结构包括铁电材料，并且第二晶体管的栅极结构不包括铁电材料。

公开(公告)号：US20150372100A1

公开(公告)日：2015-12-24

申请号：US14309586

申请日：2014-06-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823814 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits having improved contacts and improved methods for fabricating integrated circuits having contacts are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a source/drain region. The method deposits an interlayer dielectric material over the semiconductor substrate. Further, the method etches the interlayer dielectric material to form a hole defining an exposed portion of the source/drain region. The method includes forming a contact forming a contact in the hole over the exposed portion of the source/drain region and forming an interconnect in the hole over the contact.

Abstract translation: 提供具有改进的接触的集成电路和用于制造具有触点的集成电路的改进方法。 在一个实施例中，一种用于制造集成电路的方法包括：提供具有源极/漏极区域的半导体衬底。 该方法在半导体衬底上沉积层间电介质材料。 此外，该方法蚀刻层间电介质材料以形成限定源极/漏极区域的暴露部分的孔。 该方法包括在源极/漏极区域的暴露部分上形成在孔中形成接触的接触，并且在接触件上方的孔中形成互连。

公开(公告)号：US09219013B2

公开(公告)日：2015-12-22

申请号：US13799239

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Martin Gerhardt ,  Stefan Flachowsky ,  Matthias Kessler

IPC: H01L21/8238 ,  H01L21/265 ,  H01L29/66 ,  H01L29/10 ,  H01L21/8234

CPC classification number: H01L21/8238 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1083 ,  H01L29/6659

Abstract: When forming semiconductor devices including transistors with different threshold voltages, the different threshold voltages of transistors of the same conductivity type are substantially defined by performing different halo implantations. As the other implantations performed typically in the same manufacturing step, such as pre-amorphization, source and drain extension implantation and extra diffusion engineering implantations, may be identical for different threshold voltages, these implantations, in addition to a common halo base implantation, may be performed for all transistors of the same conductivity type in a common implantation sequence. Higher threshold voltages of specific transistors may be subsequently achieved by an additional low-dose halo implantation while the other transistors are covered by a resist mask. Thus, the amount of atoms of the implant species in the required resist masks is reduced so that removal of the resist masks is facilitated. Furthermore, the number of implantation steps is decreased compared to conventional manufacturing processes.

Abstract translation: 当形成包括具有不同阈值电压的晶体管的半导体器件时，相同导电类型的晶体管的不同阈值电压基本上通过执行不同的光晕注入来定义。 由于通常在同一制造步骤中进行的其它植入，例如预非晶化，源极和漏极延伸注入和额外的扩散工程注入，对于不同的阈值电压可以是相同的，除了常见的晕基植入之外，这些植入可以 在同一种植入序列中对相同导电类型的所有晶体管执行。 随后可以通过额外的低剂量晕圈注入实现特定晶体管的较高阈值电压，而另一晶体管被抗蚀剂掩模覆盖。 因此，所需抗蚀剂掩模中的注入物种的原子量减少，从而便于除去抗蚀剂掩模。 此外，与常规制造工艺相比，植入步骤的数量减少。