公开(公告)号：US09110116B2

公开(公告)日：2015-08-18

申请号：US14494095

申请日：2014-09-23

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Pascal Fornara

IPC: H01L23/58 ,  G01R27/26 ,  G11C27/02 ,  H01L21/84 ,  H01L23/522 ,  H01L27/08 ,  H01L27/12 ,  H01L49/02 ,  H01L29/94 ,  G04F13/00 ,  G01R17/02 ,  G11C11/24 ,  H01G4/005 ,  H01G4/018 ,  H01G4/38

CPC classification number: G01R27/2605 ,  G01R17/02 ,  G04F10/10 ,  G04F13/00 ,  G11C11/24 ,  G11C27/024 ,  H01G4/005 ,  H01G4/018 ,  H01G4/38 ,  H01L21/84 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/1203 ,  H01L28/40 ,  H01L29/94 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A charge flow circuit for a time measurement, including a plurality of elementary capacitive elements electrically in series, each elementary capacitive element leaking through its dielectric space.

Abstract translation: 一种用于时间测量的电荷流动电路，包括电串联的多个基本电容元件，每个元件电容元件通过其介电空间泄漏。

公开(公告)号：US08941205B2

公开(公告)日：2015-01-27

申请号：US13646828

申请日：2012-10-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara

IPC: H01L29/66 ,  H01L35/30 ,  H01L27/16 ,  H01L35/00 ,  H01L37/00

CPC classification number: H01L35/30 ,  H01L27/16 ,  H01L35/00 ,  H01L37/00

Abstract: An integrated circuit may include a region containing a thermoelectric material and be configured to be subjected to a temperature gradient resulting from a flow of an electric current in a part of the integrated circuit during its operation, and an electrically conducting output coupled to the region for delivering the electrical energy produced by thermoelectric material.

Abstract translation: 集成电路可以包括含有热电材料的区域，并且被配置为经受在其工作期间在集成电路的一部分中的电流流动导致的温度梯度，以及耦合到该区域的导电输出 传递由热电材料产生的电能。

公开(公告)号：US20140367784A1

公开(公告)日：2014-12-18

申请号：US14300663

申请日：2014-06-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Giulhem Bouton ,  Pascal Fornara

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0653 ,  H01L21/76224 ,  H01L21/76229 ,  H01L23/5226 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66568 ,  H01L29/7846 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.

Abstract translation: 集成电路包括衬底和至少一个NMOS晶体管，其在衬底中具有由绝缘区域包围的有源区域。 绝缘区域形成为包括至少一个区域，其中绝缘区域具有通过由基板的一部分形成的分离区域彼此分离的两个绝缘区域。

公开(公告)号：US20140266562A1

公开(公告)日：2014-09-18

申请号：US14289784

申请日：2014-05-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Antonio Di-Giacomo ,  Christian Rivero ,  Pascal Fornara

IPC: H01H1/00

CPC classification number: H01H1/0036 ,  H01H61/00 ,  H01H2001/0068 ,  H01H2037/008 ,  H01H2061/006 ,  H01H2061/008

Abstract: An integrated circuit, comprising an electrical-switching mechanical device in a housing having at least one first thermally deformable assembly including a beam held in at least two different locations by at least two arms secured to edges of the housing, the beam and the arms being metallic and situated within the same first metallization level and an electrically conductive body, wherein the said first thermally deformable assembly has at least one first configuration at a first temperature and a second configuration when at least one is at a second temperature different from the first temperature, wherein the beam is at a distance from the body in the first configuration and in contact with the said body and immobilized by the said body in the second configuration and establishing or prohibiting an electrical link passing through the body and through the beam.

Abstract translation: 一种集成电路，包括壳体中的电切换机械装置，其具有至少一个第一热变形组件，所述组件包括通过固定到所述壳体的边缘的至少两个臂固定在至少两个不同位置的梁，所述梁和所述臂是 金属并位于相同的第一金属化水平和导电体内，其中所述第一热变形组件在第一温度和第二构型具有至少一个第一构型，当至少一个处于与第一温度不同的第二温度时 ，其中所述梁在所述第一构造中与所述主体一定距离并且与所述主体接触并且以所述第二构造被所述主体固定，并且建立或禁止穿过所述主体并通过所述梁的电连杆。

公开(公告)号：US08830761B2

公开(公告)日：2014-09-09

申请号：US13786202

申请日：2013-03-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Olivier Pizzuto ,  Stephan Niel ,  Philippe Boivin ,  Pascal Fornara ,  Laurent Lopez ,  Arnaud Regnier

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/14 ,  G11C16/08 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  G11C16/04 ,  G11C11/56 ,  G11C8/12

CPC classification number: G11C16/26 ,  G11C8/12 ,  G11C11/5642 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/14 ,  G11C16/24 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/7881

Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.

Abstract translation: 本公开涉及一种读取和写入存储单元的方法，每个存储单元包括与选择晶体管串联的电荷累积晶体管，包括将选择电压施加到存储器单元的选择晶体管的栅极; 将读取电压施加到存储单元的电荷累积晶体管的控制栅极; 将选择电压施加到耦合到相同位线的第二存储器单元的选择晶体管的栅极; 以及向第二存储单元的电荷累积晶体管的控制栅极施加抑制电压，以保持晶体管处于阻塞状态。

公开(公告)号：US20140167908A1

公开(公告)日：2014-06-19

申请号：US14185310

申请日：2014-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero ,  Antonio di-Giacomo

IPC: H01H37/52

CPC classification number: H01H37/52 ,  B81B3/0024 ,  G01K3/005 ,  G01K5/486 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit comprising a mechanical device for electrical switching comprising a first assembly being thermally deformable and having a beam held at at least two different locations by at least two arms, the beam and the arms being metal and disposed within the same metallization level, and further comprising at least one electrically conducting body. The first assembly has a first configuration at a first temperature and a second configuration at a second temperature different from the first temperature. The beam is out of contact with the electrically conducting body in one configuration in contact with the body in the other configuration. The beam establishes or breaks an electrical link passing through the said at least one electrically conducting body and through the said beam in the different configurations.

Abstract translation: 一种集成电路，包括用于电开关的机械装置，包括可热变形的第一组件，并且具有通过至少两个臂保持在至少两个不同位置处的梁，所述梁和所述臂是金属并且设置在相同的金属化水平内，以及 还包括至少一个导电体。 第一组件具有在第一温度下的第一构型和在与第一温度不同的第二温度下的第二构型。 在与另一种结构中的身体接触的一种结构中，光束与导电体脱离接触。 光束建立或断开通过所述至少一个导电体并通过所述光束的不同构造的电连接。

公开(公告)号：US08704327B2

公开(公告)日：2014-04-22

申请号：US13688022

申请日：2012-11-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio di-Giacomo

IPC: H01L31/058

CPC classification number: H01L28/40 ,  G01K5/486 ,  G01K5/62

Abstract: An integrated circuit, comprising a capacitive device having a thermally variable capacitive value and comprising a thermally deformable assembly disposed within an enclosure, and comprising an electrically-conducting fixed body and a beam held at least two different locations by at least two arms rigidly attached to edges of the enclosure, the beam and the arms being metal and disposed within the first metallization level. A part of the said thermally deformable assembly may form a first electrode of the capacitive device and a part of the said fixed body may form a second electrode of the capacitive device. The thermally deformable assembly has a plurality of configurations corresponding respectively to various temperatures of the said assembly and resulting in a plurality of distances separating the two electrodes and various capacitive values in the capacitive device corresponding to the plurality of distances.

Abstract translation: 一种集成电路，包括具有热可变电容值的电容性装置，并且包括设置在外壳内的热变形组件，并且包括导电固定体和通过至少两个不同位置保持的梁，刚性地连接至 外壳的边缘，梁和臂是金属的并且设置在第一金属化层内。 所述热变形组件的一部分可以形成电容性装置的第一电极，并且所述固定体的一部分可以形成电容性装置的第二电极。 热变形组件具有分别对应于所述组件的各种温度的多个构造，并且导致分离两个电极的多个距离和对应于多个距离的电容性装置中的各种电容值。

公开(公告)号：US12272509B2

公开(公告)日：2025-04-08

申请号：US16680940

申请日：2019-11-12

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Christian Rivero ,  Pascal Fornara ,  Antonio Di-Giacomo ,  Brice Arrazat

IPC: H01H59/00 ,  B81C1/00 ,  H01H1/00 ,  H01H57/00 ,  H01L21/822 ,  H01L27/06 ,  H01L23/522

Abstract: Methods of operating a switching device are provided. The switching device is formed in an interconnect, the interconnect including a plurality of metallization levels, and has an assembly that includes a beam held by a structure. The beam and structure are located within the same metallization level. Locations of fixing of the structure on the beam are arranged so as to define for the beam a pivot point situated between these fixing locations. The structure is substantially symmetric with respect to the beam and to a plane perpendicular to the beam in the absence of a potential difference. The beam is able to pivot in a first direction in the presence of a first potential difference applied between a first part of the structure and to pivot in a second direction in the presence of a second potential difference applied between a second part of the structure.

公开(公告)号：US12021074B2

公开(公告)日：2024-06-25

申请号：US17516920

申请日：2021-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Roberto Simola

IPC: H01L29/40 ,  H01L21/70 ,  H01L27/01 ,  H10B41/41 ,  H10B41/42

CPC classification number: H01L27/016 ,  H01L21/707 ,  H10B41/41 ,  H10B41/42

Abstract: An integrated circuit includes a semiconductor substrate, a conductive layer above a front face of the substrate, a first metal track in a first metal level, and a pre-metal dielectric region located between the conductive layer and the first metal level. A metal-insulator-metal-type capacitive structure is located in a trench within the pre-metal dielectric region. The capacitive structure includes a first metal layer electrically connected with the conductive layer, a second metal layer electrically connected with the first metal track, and a dielectric layer between the first metal layer and the second metal layer.

公开(公告)号：US11088241B2

公开(公告)日：2021-08-10

申请号：US16739753

申请日：2020-01-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara

IPC: H01L29/00 ,  H01L29/04 ,  H01L29/66 ,  H01L29/861 ,  H01L29/868

Abstract: A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.