公开(公告)号：US06483137B2

公开(公告)日：2002-11-19

申请号：US09942205

申请日：2001-08-29

申请人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Tang Hsu

发明人： Tingkai Li ,  Fengyan Zhang ,  Yoshi Ono ,  Sheng Tang Hsu

IPC分类号： H01L2976

CPC分类号： H01L21/31691 ,  C23C16/40 ,  H01L21/31604 ,  Y10S438/933 ,  Y10T428/12674 ,  Y10T428/12701 ,  Y10T428/12875

摘要： A ferroelectric Pb5Ge3O11 (PGO) thin film is provided with a metal organic vapor deposition (MOCVD) process and RTP (Rapid Thermal Process) annealing techniques. The PGO film is substantially crystallization with c-axis orientation at temperature between 450 and 650° C. The PGO film has an average grain size of about 0.5 microns, with a deviation in grain size uniformity of less than 10%. Good ferroelectric properties are-obtained for a 150 nm thick film with Ir electrodes. The films also show fatigue-free characteristics: no fatigue was observed up to 1×109 switching cycles. The leakage currents increase with increasing applied voltage, and are about 3.6×10−7 A/cm2 at 100 kV/cm. The dielectric constant shows a behavior similar to most ferroelectric materials, with a maximum dielectric constant of about 45. These high quality MOCVD Pb5Ge3O11 films can be used for high density single transistor ferroelectric memory applications because of the homogeneity of the PGO film grain size.

摘要翻译： 铁电Pb5Ge3O11（PGO）薄膜提供金属有机气相沉积（MOCVD）工艺和RTP（快速热处理）退火技术。 PGO膜在450-650℃的温度下基本上以c轴取向结晶.PGO膜的平均粒径为约0.5微米，晶粒尺寸均匀度的偏差小于10％。 对于具有Ir电极的150nm厚的膜，获得良好的铁电性能。 这些胶片还显示出无疲劳特性：在1x109个开关周期内没有观察到疲劳。 泄漏电流随着施加电压的增加而增加，在100kV / cm时为约3.6×10 -7 A / cm 2。 介电常数表现出类似于大多数铁电材料的行为，其最大介电常数为约45.这些高质量的MOCVD Pb5Ge3O11膜可用于高密度单晶硅铁氧体存储器应用，因为PGO膜晶粒尺寸的均匀性。

公开(公告)号：US06350699B1

公开(公告)日：2002-02-26

申请号：US09584407

申请日：2000-05-30

申请人： Jer-shen Maa ,  Fengyan Zhang

发明人： Jer-shen Maa ,  Fengyan Zhang

IPC分类号： H01L2100

CPC分类号： H01L21/32136 ,  C23F4/00

摘要： A method of anisotropically etching metals, especially iridium, platinum, ruthenium, osmium, and rhenium using a non-chlorofluorocarbon, fluorine-based chemistry. A substrate having metal deposited thereon, is inserted into an ECR plasma etch chamber and heated. A fluorine containing gas, such as, carbon tetrafluoride (CF4), nitrogen trifluoride (NF3) or sulfur hexafluoride (SF6) is introduced into the chamber and ionized to form a plasma. Fluorine ions within the plasma strike, or contact, the metal to form volatile metal-fluorine compounds. The metal-fluorine compounds are exhausted away from the substrate to reduce, or eliminate, redeposition of etch reactants.

摘要翻译： 使用非氯氟烃氟基化学物质各向异性蚀刻金属，特别是铱，铂，钌，锇和铼的方法。 将其上沉积有金属的衬底插入到ECR等离子体蚀刻室中并加热。 将四氟化碳（CF 4），三氟化氮（NF 3）或六氟化硫（SF 6）等含氟气体引入室内并离子化形成等离子体。 等离子体内的氟离子冲击，或接触金属，形成挥发性金属氟化合物。 金属 - 氟化合物从衬底排出，以减少或消除蚀刻反应物的再沉积。

公开(公告)号：US09371226B2

公开(公告)日：2016-06-21

申请号：US13019879

申请日：2011-02-02

申请人： Robert V. Fox ,  Fengyan Zhang ,  Rene G. Rodriguez ,  Joshua J. Pak ,  Chivin Sun

发明人： Robert V. Fox ,  Fengyan Zhang ,  Rene G. Rodriguez ,  Joshua J. Pak ,  Chivin Sun

IPC分类号： H01L31/02 ,  H01L31/18 ,  C01B17/00 ,  B82Y30/00 ,  C01G15/00 ,  H01L31/032 ,  H01L31/0392 ,  H01L31/0749

CPC分类号： B82Y30/00 ,  C01G15/006 ,  C01P2002/72 ,  C01P2002/84 ,  C01P2004/62 ,  C01P2004/64 ,  C01P2006/40 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/541

摘要： Single source precursors or pre-copolymers of single source precursors are subjected to microwave radiation to form particles of a I-III-VI2 material. Such particles may be formed in a wurtzite phase and may be converted to a chalcopyrite phase by, for example, exposure to heat. The particles in the wurtzite phase may have a substantially hexagonal shape that enables stacking into ordered layers. The particles in the wurtzite phase may be mixed with particles in the chalcopyrite phase (i.e., chalcopyrite nanoparticles) that may fill voids within the ordered layers of the particles in the wurtzite phase thus produce films with good coverage. In some embodiments, the methods are used to form layers of semiconductor materials comprising a I-III-VI2 material. Devices such as, for example, thin-film solar cells may be fabricated using such methods.

摘要翻译： 将单源前体或单源前体的预共聚物进行微波辐射以形成I-III-VI2材料的颗粒。 这样的颗粒可以以纤锌矿相形成，并且可以通过例如暴露于热而转变成黄铜矿相。 纤锌矿相中的颗粒可以具有基本上六边形的形状，其能够堆叠成有序层。 纤锌矿相中的颗粒可以与黄铜矿相中的颗粒（即，黄铜矿纳米颗粒）混合，其可以填充纤锌矿相中颗粒的有序层内的空隙，从而产生具有良好覆盖率的膜。 在一些实施例中，所述方法用于形成包含I-III-VI2材料的半导体材料层。 可以使用这样的方法来制造诸如薄膜太阳能电池的装置。

公开(公告)号：US20070167008A1

公开(公告)日：2007-07-19

申请号：US11717818

申请日：2007-03-14

申请人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

发明人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

IPC分类号： H01L21/44

CPC分类号： H01L27/101 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.

摘要翻译： 提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。 该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。 通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。 一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。 使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

公开(公告)号：US20070111368A1

公开(公告)日：2007-05-17

申请号：US11280423

申请日：2005-11-16

申请人： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

发明人： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

IPC分类号： H01L51/40 ,  H01L21/00

CPC分类号： H01L51/4213 ,  B82Y10/00 ,  H01L51/0046 ,  H01L51/0048 ,  H01L51/4226 ,  H01L51/4233 ,  H01L51/441 ,  Y02E10/52 ,  Y02E10/549

摘要： A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).

摘要翻译： 提供光伏（PV）结构以及用于形成具有导电纳米线阵列电极的PV结构的方法。 该方法包括：形成具有导电纳米线的底电极; 形成覆盖在纳米线上的第一掺杂剂型（即n型）的第一半导体层; 形成与所述第一掺杂剂类型（即，p型）相反的第二掺杂剂类型的第二半导体层，所述第二掺杂剂类型覆盖所述第一半导体层; 以及形成覆盖所述第二半导体层的顶部电极。 第一和第二半导体层可以是诸如导电聚合物，具有富勒烯衍生物的共轭聚合物和诸如CdSe，CdS，二氧化钛或ZnO的无机材料的材料。 导电纳米线可以是诸如IrO 2，In 2 O 3，SnO 2，或铟的材料 氧化锡（ITO）。

公开(公告)号：US20060180817A1

公开(公告)日：2006-08-17

申请号：US11061946

申请日：2005-02-17

申请人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

发明人： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

IPC分类号： H01L27/15

CPC分类号： H05B33/145

摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.

摘要翻译： 提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。 该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。 纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。 通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。 在一个方面，Si磷光体层是SRSO层。 响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

公开(公告)号：US20060088974A1

公开(公告)日：2006-04-27

申请号：US10971387

申请日：2004-10-21

申请人： Wei-Wei Zhuang ,  David Evans ,  Fengyan Zhang ,  Sheng Hsu

发明人： Wei-Wei Zhuang ,  David Evans ,  Fengyan Zhang ,  Sheng Hsu

IPC分类号： H01L21/20 ,  H01L21/00

CPC分类号： H01L45/1608 ,  C23C18/1216 ,  C23C18/1225 ,  C23C18/1283 ,  C23C18/1295 ,  H01L21/31691 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.

摘要翻译： 制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

公开(公告)号：US20060040413A1

公开(公告)日：2006-02-23

申请号：US10923381

申请日：2004-08-20

申请人： Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

发明人： Fengyan Zhang ,  Bruce Ulrich ,  Lisa Stecker ,  Sheng Hsu

IPC分类号： H01L21/00

CPC分类号： H01L21/32139 ,  H01L21/32136 ,  H01L27/1085 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/65

摘要： A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.

公开(公告)号：US20050243630A1

公开(公告)日：2005-11-03

申请号：US11174034

申请日：2005-07-01

申请人： Sheng Hsu ,  Fengyan Zhang

发明人： Sheng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  G11C7/00

CPC分类号： H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

摘要翻译： 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。

公开(公告)号：US20050124112A1

公开(公告)日：2005-06-09

申请号：US10730726

申请日：2003-12-08

申请人： Sheng Hsu ,  Fengyan Zhang

发明人： Sheng Hsu ,  Fengyan Zhang

IPC分类号： H01L21/28 ,  G11C11/15 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8239 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/105 ,  H01L27/115 ,  H01L27/22 ,  H01L27/24 ,  H01L29/68 ,  H01L43/08 ,  H01L45/00 ,  H01L21/8242

CPC分类号： H01L27/105 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/52 ,  H01L27/1052 ,  H01L27/112 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

摘要： An asymmetric-area memory cell, and a fabrication method for forming an asymmetric-area memory cell, are provided. The method comprises: forming a bottom electrode having an area; forming a CMR memory film overlying the bottom electrode, having an asymmetric area; and, forming a top electrode having an area, less than the bottom electrode area, overlying the CMR film. In one aspect, the CMR film has a first area adjacent the top electrode and a second area, greater than the first area, adjacent the bottom electrode. Typically, the CMR film first area is approximately equal to the top electrode area, although the CMR film second area may be less than the bottom electrode area.

摘要翻译： 提供了一种不对称区域存储单元和用于形成非对称区域存储单元的制造方法。 该方法包括：形成具有面积的底部电极; 形成覆盖在底部电极上的具有不对称区域的CMR存储膜; 并且形成覆盖CMR膜的具有小于底部电极区域的面积的顶部电极。 在一个方面，CMR膜具有邻近顶部电极的第一区域和与底部电极相邻的大于第一区域的第二区域。 通常，尽管CMR膜的第二区域可能小于底部电极区域，但是CMR膜的第一区域大致等于顶部电极区域。