公开(公告)号：US09748389B1

公开(公告)日：2017-08-29

申请号：US15187976

申请日：2016-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yang Lee ,  Tzu-Hsiang Hsu ,  Ting-Yeh Chen ,  Feng-Cheng Yang

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L27/11 ,  H01L21/84

CPC classification number: H01L29/7848 ,  H01L21/845 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes receiving a precursor having a substrate and first and second pluralities of gate structures, the first pluralities having a greater pitch than the second pluralities. The method further includes depositing a dielectric layer covering the substrate and the first and second pluralities; and performing an etching process to the dielectric layer. The etching process removes a first portion of the dielectric layer over the substrate, while a second portion of the dielectric layer remains over sidewalls of the first and second pluralities. The second portion of the dielectric layer is thicker over the sidewalls of the second plurality than over the sidewalls of the first plurality. The method further includes etching the substrate to form third and fourth pluralities of recesses adjacent the first and second pluralities, respectively; and epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities, respectively.

公开(公告)号：US09570556B1

公开(公告)日：2017-02-14

申请号：US15060270

申请日：2016-03-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Yang Lee ,  Feng-Cheng Yang ,  Ting-Yeh Chen

IPC: H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L29/08 ,  H01L29/24 ,  H01L29/267 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/762 ,  H01L29/0649 ,  H01L29/785 ,  Y02E10/50

Abstract: A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure. The first fin structure and the second fin structure are both disposed over the substrate, and extend in a first direction in plan view. The gate structure is disposed over parts of the first and second fin structures, and extends in a second direction crossing the first direction in plan view. A first void is formed in the source/drain structure, and a second void is formed in the source/drain structure and located above the first void.

Abstract translation: 半导体器件包括设置在衬底上的隔离层，第一和第二鳍结构，栅极结构，源极/漏极结构。 第一翅片结构和第二翅片结构均布置在基底上，并且在俯视图中沿第一方向延伸。 栅极结构设置在第一和第二鳍结构的一部分上，并且在平面图中沿与第一方向交叉的第二方向延伸。 在源极/漏极结构中形成第一空隙，并且在源极/漏极结构中形成第二空隙并且位于第一空隙之上。

公开(公告)号：US12249640B2

公开(公告)日：2025-03-11

申请号：US18524417

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/78 ,  H01L21/225 ,  H01L21/265 ,  H01L29/165 ,  H01L29/66

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20240381656A1

公开(公告)日：2024-11-14

申请号：US18783024

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C11/22 ,  G11C11/56 ,  H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US20240347616A1

公开(公告)日：2024-10-17

申请号：US18661969

申请日：2024-05-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiu Liu ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Yen-Ting Chen

IPC: H01L29/51 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/515 ,  H01L21/311 ,  H01L27/0886 ,  H01L29/6653

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

公开(公告)号：US20240258429A1

公开(公告)日：2024-08-01

申请号：US18635834

申请日：2024-04-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-An Lin ,  Wei-Yuan Lu ,  Feng-Cheng Yang ,  Tzu-Ching Lin ,  Li-Li Su

IPC: H01L29/78 ,  A61B5/15 ,  G01N1/14 ,  G01N33/49 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/66

CPC classification number: H01L29/785 ,  A61B5/150099 ,  A61B5/150992 ,  G01N1/14 ,  G01N33/4915 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/045 ,  H01L29/7853

Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.

公开(公告)号：US20240186372A1

公开(公告)日：2024-06-06

申请号：US18439095

申请日：2024-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Bo-Yu Lai ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yih-Ann Lin ,  Yen-Ming Chen

IPC: H01L29/06 ,  H01L21/764 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/10 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76841 ,  H01L21/76897 ,  H01L21/823864 ,  H01L21/823871 ,  H01L23/10 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681

Abstract: In one example aspect, a method for integrated circuit (IC) fabrication comprises providing a device structure including a substrate, a source/drain (S/D) feature on the substrate, a gate stack on the substrate, a contact hole over the S/D feature; and a dummy feature over the S/D feature and between the gate stack and the contact hole. The method further comprises forming in the contact hole a contact plug that is electrically coupled to the S/D feature, and, after forming the contact plug, selectively removing the dummy feature to form an air gap that extends higher than a top surface of the gate stack. The method further comprises forming over the contact plug a seal layer that covers the air gap.

公开(公告)号：US11984489B2

公开(公告)日：2024-05-14

申请号：US17991560

申请日：2022-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Hsiu Liu ,  Feng-Cheng Yang ,  Tsung-Lin Lee ,  Wei-Yang Lee ,  Yen-Ming Chen ,  Yen-Ting Chen

IPC: H01L29/51 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/515 ,  H01L21/311 ,  H01L27/0886 ,  H01L29/6653

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

公开(公告)号：US20240097010A1

公开(公告)日：2024-03-21

申请号：US18524417

申请日：2023-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/265 ,  H01L29/165

CPC classification number: H01L29/66803 ,  H01L21/225 ,  H01L21/26526 ,  H01L29/165 ,  H01L29/66818

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US11917803B2

公开(公告)日：2024-02-27

申请号：US17859757

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Feng-Ching Chu ,  Wei-Yang Lee ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H10B10/12 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/31053 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H10B10/18

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.