公开(公告)号：US09484453B2

公开(公告)日：2016-11-01

申请号：US14845128

申请日：2015-09-03

申请人： Alpha and Omega Semiconductor Incorporated

发明人： Hamza Yilmaz ,  Madhur Bobde ,  Hong Chang ,  Yeeheng Lee ,  Daniel Calafut ,  Jongoh Kim ,  Sik Lui ,  John Chen

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/06 ,  H01L27/02 ,  H01L29/45 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/7813 ,  H01L27/0251 ,  H01L29/0619 ,  H01L29/0696 ,  H01L29/0856 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/6656 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L29/7827

摘要： Aspects of the present disclosure describe a high density trench-based power. The active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. A lightly doped sub-body layer may be formed below a body region between two or more adjacent active device structures of the plurality. The sub-body layer extends from a depth of the upper portion of the gate oxide to a depth of the lower portion of the gate oxide It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

摘要翻译： 本公开的方面描述了高密度基于沟槽的功率。 有源器件可以具有两步栅极氧化物。 下部可以具有比栅极氧化物的上部的厚度大的厚度。 轻掺杂子体层可以形成在多个相邻的有源器件结构之间的体区之下。 子体层从栅极氧化物的上部的深度延伸到栅极氧化物的下部的深度。强调该抽象被提供以符合要求抽象的规则，其将允许搜索者或其他 读者快速确定技术披露的主题。 提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

公开(公告)号：US09484444B2

公开(公告)日：2016-11-01

申请号：US12110621

申请日：2008-04-28

申请人： Shigeru Kusunoki ,  Koichi Mochizuki ,  Minoru Kawakami

发明人： Shigeru Kusunoki ,  Koichi Mochizuki ,  Minoru Kawakami

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L27/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7813 ,  H01L27/0611 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4232 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/66333 ,  H01L29/7395 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode to form a resistance to a current flowing through the electrode, and is arranged in the first trench with the insulating film therebetween. Thereby, the semiconductor device can have a resistance element that has a small footprint and can pass a large current with high reliability.

摘要翻译： 半导体器件具有半导体衬底，绝缘膜，半导体元件和电阻元件。 半导体衬底具有第一沟槽。 绝缘膜覆盖第一沟槽的内表面。 半导体元件具有电极。 电阻元件电连接到电极以形成对流过电极的电流的电阻，并且布置在第一沟槽中，其间具有绝缘膜。 因此，半导体器件可以具有占地面积小的电阻元件，并且可以高可靠性地传递大电流。

公开(公告)号：US09431550B2

公开(公告)日：2016-08-30

申请号：US13308375

申请日：2011-11-30

申请人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

发明人： Qufei Chen ,  Robert Xu ,  Kyle Terrill ,  Deva Pattanayak

IPC分类号： H01L27/12 ,  H01L29/76 ,  H01L29/866 ,  H01L27/06 ,  H01L27/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02

CPC分类号： H01L29/7813 ,  H01L27/0255 ,  H01L27/0629 ,  H01L27/0814 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the present invention include a method of manufacturing a trench transistor. The method includes forming a substrate of a first conductivity type and implanting a dopant of a second conductivity type, forming a body region of the substrate. The method further includes forming a trench in the body region and depositing an insulating layer in the trench and over the body region wherein the insulating layer lines the trench. The method further includes filling the trench with polysilicon forming a top surface of the trench and forming a diode in the body region wherein a portion of the diode is lower than the top surface of the trench.

公开(公告)号：US20160211757A1

公开(公告)日：2016-07-21

申请号：US14600708

申请日：2015-01-20

申请人： Infineon Technologies Austria AG

发明人： Cesar Augusto Braz ,  David Laforet

IPC分类号： H02M3/335

CPC分类号： H02M3/33592 ,  H01L25/03 ,  H01L27/02 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/407 ,  H01L29/66356 ,  H01L29/7391 ,  H01L29/7804 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/861 ,  H01L29/872 ,  H02M2001/0054 ,  H02M2001/346 ,  H03K17/145 ,  H03K2217/0036 ,  Y02B70/1475 ,  Y02B70/1491

摘要： A synchronous rectifier is described that includes a transistor device that has a gate terminal, a source terminal, a drain terminal, and a field-plate electrode. The field-plate electrode of the transistor device includes an integrated diode. The integrated diode is configured to discharge a parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier. In some examples, the integrated diode is also configured to charge the parasitic capacitance of the transistor device during each switching operation of the synchronous rectifier.

摘要翻译： 描述了一种同步整流器，其包括具有栅极端子，源极端子，漏极端子和场板电极的晶体管器件。 晶体管器件的场板电极包括集成二极管。 集成二极管被配置为在同步整流器的每个开关操作期间放电晶体管器件的寄生电容。 在一些示例中，集成二极管还被配置为在同步整流器的每个开关操作期间对晶体管器件的寄生电容进行充电。

公开(公告)号：US20160163689A1

公开(公告)日：2016-06-09

申请号：US14959276

申请日：2015-12-04

申请人： Infineon Technologies AG

发明人： Johannes Georg Laven ,  Christian Jaeger ,  Joachim Mahler ,  Daniel Pedone ,  Anton Prueckl ,  Hans-Joachim Schulze ,  Andre Schwagmann ,  Patrick Schwarz

IPC分类号： H01L27/02 ,  H01L29/78

CPC分类号： H01L27/0255 ,  H01C7/04 ,  H01L29/7803 ,  H01L29/7805 ,  H01L29/7808 ,  H01L29/7813 ,  H01L45/00

摘要： A semiconductor device includes a first load terminal electrically coupled to a source zone of a transistor cell. A gate terminal is electrically coupled to a gate electrode which is capacitively coupled to a body zone of the transistor cell. The source and body zones are formed in a semiconductor portion. A thermoresistive element is thermally connected to the semiconductor portion and is electrically coupled between the gate terminal and the first load terminal. Above a maximum operation temperature specified for the semiconductor device, an electric resistance of the thermoresistive element decreases by at least two orders of magnitude within a critical temperature span of at most 50 Kelvin.

摘要翻译： 半导体器件包括电耦合到晶体管单元的源极区的第一负载端子。 栅极端子电耦合到电容耦合到晶体管单元的体区的栅电极。 源区和体区形成在半导体部分中。 热电阻元件热连接到半导体部分，并且电连接在栅极端子和第一负载端子之间。 在对于半导体器件规定的最大工作温度之上，耐温元件的电阻在至多50开尔文的临界温度范围内降低至少两个数量级。

公开(公告)号：US20160148923A1

公开(公告)日：2016-05-26

申请号：US15001767

申请日：2016-01-20

申请人： Renesas Electronics Corporation

发明人： Yoshito NAKAZAWA ,  Yuji YATSUDA

IPC分类号： H01L27/02 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L21/28008 ,  H01L21/28556 ,  H01L27/0255 ,  H01L29/0696 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device having a field-effect transistor, including a trench in a semiconductor substrate, a first insulating film in the trench, an intrinsic polycrystalline silicon film over the first insulating film, and first conductivity type impurities in the intrinsic polycrystalline silicon film to form a first conductive film. The first conductive film is etched to form a first gate electrode in the trench. A second insulating film is also formed in the trench above the first insulating film and the first gate electrode, and a first conductivity type doped polycrystalline silicon film, having higher impurity concentration than the first gate electrode is formed over the second insulating film. The doped polycrystalline silicon film is provided in an upper part of the trench to form a second gate electrode.

摘要翻译： 一种具有场效应晶体管的半导体器件，包括半导体衬底中的沟槽，沟槽中的第一绝缘膜，第一绝缘膜上的本征多晶硅膜，以及本征多晶硅膜中的第一导电型杂质，以形成 第一导电膜。 蚀刻第一导电膜以在沟槽中形成第一栅电极。 在第二绝缘膜上形成有在第一绝缘膜和第一栅电极上方的沟槽中的第二绝缘膜，并且在第二绝缘膜上形成杂质浓度高于第一栅电极的第一导电型掺杂多晶硅膜。 掺杂多晶硅膜设置在沟槽的上部，以形成第二栅电极。

公开(公告)号：US20160111490A1

公开(公告)日：2016-04-21

申请号：US14976873

申请日：2015-12-21

申请人： RENESAS ELECTRONICS CORPORATION ,  Renesas Eastern Japan Semiconductor, Inc.

发明人： Hiroshi INAGAWA ,  Nobuo MACHIDA ,  Kentaro OISHI

IPC分类号： H01L29/06 ,  H01L29/51 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/7808 ,  H01L29/0615 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/511 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7821 ,  H01L29/7827

摘要： In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

公开(公告)号：US20160013311A1

公开(公告)日：2016-01-14

申请号：US14862236

申请日：2015-09-23

申请人： Infineon Technologies AG

发明人： Peter Nelle ,  Markus Zundel

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/7808 ,  H01L27/0629 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/7813 ,  H01L29/8613

摘要： One embodiment of a semiconductor device includes a dense trench transistor cell array. The dense trench transistor cell array includes a plurality of transistor cells in a semiconductor body. A width w3 of a transistor mesa region of each of the plurality of transistor cells and a width w1 of a first trench of each of the plurality of transistor cells satisfy the following relationship: w3

摘要翻译： 半导体器件的一个实施例包括致密沟槽晶体管单元阵列。 密集沟槽晶体管单元阵列包括半导体本体中的多个晶体管单元。 多个晶体管单元的晶体管台面区域的宽度w3和多个晶体管单元中的每一个的第一沟槽的宽度w1满足以下关系：w3 <1.5×w1。 半导体器件还包括半导体二极管。 至少一个半导体二极管布置在多个晶体管单元的第一和第二部分之间，并且包括邻接第二沟槽的相对壁的二极管台面区域。 第一沟槽的深度d1和第二沟槽的深度d2相差至少20％。

公开(公告)号：US09147763B2

公开(公告)日：2015-09-29

申请号：US14033941

申请日：2013-09-23

申请人： Infineon Technologies Austria AG

发明人： Hans Weber ,  Franz Hirler ,  Armin Willmeroth ,  Stefan Gamerith

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7804 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/78 ,  H01L29/7808 ,  H01L29/7811

摘要： An active area of a semiconductor body includes a first charge-compensation structure having spaced apart n-type pillar regions, and an n-type first field-stop region of a semiconductor material in Ohmic contact with a drain metallization and the n-type pillar regions and having a doping charge per area higher than a breakdown charge per area of the semiconductor material. A punch-through area of the semiconductor body includes a p-type semiconductor region in Ohmic contact with a source metallization, a floating p-type body region and an n-type second field-stop region. The floating p-type body region extends into the active area. The second field-stop region is in Ohmic contact with the first field-stop region, forms a pn-junction with the floating p-type body region, is arranged between the p-type semiconductor region and floating p-type body region, and has a doping charge per area lower than the breakdown charge per area of the semiconductor material.

摘要翻译： 半导体本体的有源区域包括具有间隔开的n型柱区域的第一电荷补偿结构和与漏极金属化和n型支柱欧姆接触的半导体材料的n型第一场致区域 并且每个区域具有高于半导体材料的每个面积的击穿电荷的掺杂电荷。 半导体本体的穿通区域包括与源极金属化，浮动p型体区域和n型第二场停止区域欧姆接触的p型半导体区域。 浮动p型体区域延伸到有源区域。 第二场停止区域与第一场停止区域欧姆接触，与浮动p型体区域形成pn结，布置在p型半导体区域和浮动p型体区域之间，以及 每个区域的掺杂电荷低于半导体材料每区域的击穿电荷。

公开(公告)号：US09136335B2

公开(公告)日：2015-09-15

申请号：US13443059

申请日：2012-04-10

申请人： Eiichi Taketani ,  Seigo Oosawa

发明人： Eiichi Taketani ,  Seigo Oosawa

IPC分类号： H01L21/335 ,  H01L29/10 ,  H01L21/28 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/336 ,  H01L21/265 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/739

CPC分类号： H01L29/1095 ,  H01L21/26586 ,  H01L21/28211 ,  H01L29/0626 ,  H01L29/0878 ,  H01L29/41766 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7808 ,  H01L29/7813

摘要： In a manufacturing method of a semiconductor device, a trench is defined in a semiconductor substrate, and an adjuster layer having a first conductivity type impurity concentration higher than a drift layer is formed at a portion of the semiconductor substrate adjacent to a bottom wall of the trench. A channel layer is formed by introducing second conductivity type impurities to a portion of the semiconductor substrate adjacent to a sidewall of the trench and between the adjustment layer and a main surface of the semiconductor substrate while restricting the channel layer from extending in a depth direction of the trench by the adjustment layer.