公开(公告)号：US20240107891A1

公开(公告)日：2024-03-28

申请号：US18526636

申请日：2023-12-01

Applicant: Everspin Technologies, Inc.

Inventor： Sanjeev AGGARWAL ,  Sarin A. DESHPANDE ,  Kerry Joseph NAGEL

IPC: H10N50/01 ,  H10B61/00

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10B61/22

Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.

公开(公告)号：US11937436B2

公开(公告)日：2024-03-19

申请号：US17285122

申请日：2019-10-29

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Han-Jong Chia ,  Sarin Deshpande ,  Ahmet Demiray

IPC: H10B61/00 ,  H10N30/50 ,  H10N35/80 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/10 ,  H10B61/00 ,  H10B61/20 ,  H10N30/50 ,  H10N35/80 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive stack includes a fixed magnetic region, one or more dielectric layers disposed on and in contact with the fixed magnetic region, and a free magnetic region disposed above the one or mom dielectric layers. The fixed magnetic region may include a first ferromagnetic region, a coupling layer, a second ferromagnetic region, a transition layer disposed, a reference layer, and at least one interfacial layer disposed above the second ferromagnetic region. Another interfacial layer may be disposed between the one or more dielectric layers and the free magnetic region.

公开(公告)号：US20240090335A1

公开(公告)日：2024-03-14

申请号：US18307633

申请日：2023-04-26

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H10N50/01 ,  B82Y25/00 ,  G01R33/00 ,  G01R33/09 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

CPC classification number: H10N50/01 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US11757451B2

公开(公告)日：2023-09-12

申请号：US17652905

申请日：2022-02-28

Applicant: Everspin Technologies, Inc.

Inventor： Dimitri Houssameddine ,  Syed M. Alam ,  Sanjeev Aggarwal

IPC: H03K19/1776 ,  G11C11/16 ,  G11C13/00 ,  H03K19/17784 ,  H03K19/17724 ,  G06F21/78

CPC classification number: H03K19/1776 ,  G11C11/1675 ,  G11C13/0069 ,  H03K19/17724 ,  H03K19/17784 ,  G06F21/78

Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.

公开(公告)号：US20230281434A1

公开(公告)日：2023-09-07

申请号：US17893462

申请日：2022-08-23

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Dimitri HOUSSAMEDDINE ,  Sanjeev AGGARWAL

IPC: G06N3/063 ,  G11C11/54 ,  G11C11/16

CPC classification number: G06N3/063 ,  G11C11/54 ,  G11C11/161

Abstract: The present disclosure is drawn to, among other things, a device comprising input circuitry; weight operation circuitry electrically connected to the input circuitry; bias operation circuitry electrically connected to the weight operation circuitry; storage circuitry electrically connected to the weight operation circuitry and the bias operation circuitry; and activation function circuitry electrically connected to the bias operation circuitry, wherein at least the weight operation circuitry, the bias operation circuitry, and the storage circuitry are located on a same chip.

公开(公告)号：US20230263071A1

公开(公告)日：2023-08-17

申请号：US17670049

申请日：2022-02-11

Applicant: Everspin Technologies, Inc.

Inventor： Sumio IKEGAWA ,  Jijun SUN ,  Monika ARORA

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

CPC classification number: H01L43/02 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetoresistive stack may include a first electrically conductive material, a fixed region having a fixed magnetic state, a free region configured to have a first magnetic state and a second magnetic state, a dielectric layer disposed between the fixed region and the free region, a spacer region, and a cap layer disposed between the spacer region and the free region. The free region may include a layer of ferromagnetic material, an insertion layer, an iPMA layer, and/or a low saturation magnetization layer.

公开(公告)号：US20230245692A1

公开(公告)日：2023-08-03

申请号：US18297793

申请日：2023-04-10

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. ALAM ,  Yaojun ZHANG ,  Frederick NEUMEYER

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1657

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US11690229B2

公开(公告)日：2023-06-27

申请号：US17131926

申请日：2020-12-23

Applicant: Everspin Technologies, Inc.

Inventor： Jijun Sun ,  Sanjeev Aggarwal ,  Han-Jong Chia ,  Jon M. Slaughter ,  Renu Whig

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  G11B5/39 ,  H01L43/10

CPC classification number: H01L27/222 ,  G11B5/3909 ,  G11C11/1673 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).

公开(公告)号：US20230047005A1

公开(公告)日：2023-02-16

申请号：US17397067

申请日：2021-08-09

Applicant: Everspin Technologies, Inc.

Inventor： Jijun SUN

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  G11C11/16

Abstract: A magnetoresistive stack may include: a fixed region having a fixed magnetic state, a spacer region, a first dielectric layer and a second dielectric layer, where both the first dielectric layer and the second dielectric layer are between the fixed region and the spacer region, and a free region between the first dielectric layer and the second dielectric layer. The free region may be configured to have a first magnetic state and a second magnetic state. The free region may include an interface layer, a multilayer structure, an insertion layer (e.g., a metallized insertion layer), one or more ferromagnetic layers (e.g., metallized ferromagnetic layers), and/or a transition layer (e.g., a metallized transition layer).

公开(公告)号：US11482570B2

公开(公告)日：2022-10-25

申请号：US17134865

申请日：2020-12-28

Applicant: Everspin Technologies, Inc.

Inventor： Kerry Joseph Nagel ,  Sanjeev Aggarwal ,  Thomas Andre ,  Sarin A. Deshpande

IPC: H01L29/82 ,  H01L43/00 ,  H01L27/22 ,  H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02

Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.