公开(公告)号：US11681342B2

公开(公告)日：2023-06-20

申请号：US17141102

申请日：2021-01-04

Applicant: Rambus Inc.

Inventor： Stephen G. Tell

IPC: G06F12/00 ,  G06F1/26 ,  G06F13/40 ,  H04L7/02 ,  G06F1/10 ,  G06F13/38 ,  G06F12/02 ,  G11C7/10 ,  H03K19/1776

CPC classification number: G06F1/26 ,  G06F1/10 ,  G06F12/0246 ,  G06F13/382 ,  G06F13/4072 ,  G11C7/1072 ,  H03K19/1776 ,  H04L7/02 ,  G06F2212/7201

Abstract: A circuit interface includes one or more processors that generate opcodes, a plurality of interface control circuits, each including a respective processing element responsive to the opcodes generated by one or more processors. Each interface control circuit corresponds to a respective link of a plurality of links of a device-to-device interface (DDI), and each link of the plurality of links of the DDI is for transmitting or receiving signals from one or more sources or one or more destinations external to the circuit.

公开(公告)号：US20230177176A1

公开(公告)日：2023-06-08

申请号：US18074225

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Evan Lawrence Erickson ,  Taeksang Song

IPC: G06F21/60 ,  G06F21/85 ,  G06F21/54

CPC classification number: G06F21/602 ,  G06F21/85 ,  G06F21/54

Abstract: A multi-processor device is disclosed. The multi-processor device includes memory interface circuitry to access external memory. A primary processor is selectively coupled to the interface circuitry. A secure processor enables/disables access to the memory interface circuitry by the primary processor based on an operating mode of the multi-processor IC chip.

公开(公告)号：US11671286B2

公开(公告)日：2023-06-06

申请号：US17298165

申请日：2019-12-10

Applicant: Rambus Inc.

Inventor： Mohammad Sadegh Jalali ,  Marcus Van Ierssel

IPC: H04L25/03

CPC classification number: H04L25/03267 ,  H04L25/03057 ,  H04L25/03146

Abstract: A receiver utilizes loop-unrolled decision feedback equalization (DFE). For each sample, two comparators, each configured with different thresholds, sample an input signal. The output of one of these comparators is selected and used as the output of the receiver and may be optionally input to additional DFE circuitry. The output of the other (non-selected) comparator is used to adjust an input offset voltage of that same comparator. Adjustments to the offset voltages of the comparators may be based on a statistical analysis of the respective outputs of the two comparators when not selected. Adjustments to the offset voltages of the comparators may be based on comparisons between the respective outputs of the two comparators when not selected to the outputs of a reference comparator that has been calibrated for minimal or zero offset.

公开(公告)号：US11669124B2

公开(公告)日：2023-06-06

申请号：US17715869

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Abhijit M. Abhyankar ,  Kun-Yung Chang ,  Frank Lambrecht

IPC: G06F1/08 ,  G11C29/02 ,  G11C29/50 ,  H04L7/00 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14 ,  G06F1/12

CPC classification number: G06F1/08 ,  G06F1/12 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C29/50012 ,  H04L7/0008 ,  H04L7/0033 ,  H04L7/0091 ,  H04L7/033 ,  H04L7/10 ,  H04L25/14 ,  H04L7/0004

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

公开(公告)号：US20230170039A1

公开(公告)日：2023-06-01

申请号：US18074188

申请日：2022-12-02

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C29/00 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

CPC classification number: G11C29/4401 ,  G11C29/88 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/76 ,  G11C29/783 ,  G11C29/52 ,  G11C2029/4402

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US20230163779A1

公开(公告)日：2023-05-25

申请号：US18070694

申请日：2022-11-29

Applicant: Rambus Inc.

Inventor： Ravi SHIVNARAINE ,  Marcus VAN IERSSEL

IPC: H03M1/68

CPC classification number: H03M1/68

Abstract: A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.

公开(公告)号：US11651823B2

公开(公告)日：2023-05-16

申请号：US16953182

申请日：2020-11-19

Applicant: Rambus Inc.

Inventor： Brent S. Haukness ,  Ian Shaeffer ,  Gary Bela Bronner

IPC: G11C16/10 ,  G06F3/06

CPC classification number: G11C16/10 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688 ,  G06F2212/7204

Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.

公开(公告)号：US11646094B2

公开(公告)日：2023-05-09

申请号：US17840765

申请日：2022-06-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/1012 ,  G06F11/1016 ,  G06F11/1032 ,  G06F11/1048 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401

Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

公开(公告)号：US20230138512A1

公开(公告)日：2023-05-04

申请号：US17989838

申请日：2022-11-18

Applicant: Rambus Inc.

Inventor： Suresh Rajan ,  Abhijit M. Abhyankar ,  Ravindranath Kollipara ,  David A. Secker

IPC: G06F3/06 ,  G06F13/16

Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.

公开(公告)号：US20230125262A1

公开(公告)日：2023-04-27

申请号：US17963065

申请日：2022-10-10

Applicant: Rambus Inc.

Inventor： Mark D. KELLAM ,  Dongyun LEE ,  Thomas VOGELSANG ,  Steven C. WOO

IPC: G02B6/293 ,  G02B6/12 ,  H04B10/50

Abstract: Command/address and timing information is distributed to buffer integrated circuits on a module using multiple wavelengths of light modulated with the same information. Each individual wavelength of modulated light carrying command/address information is received by a corresponding single buffer device that deserializes the command/address information and communicates it electrically to memory devices(s). Likewise, each individual wavelength of modulated light carrying timing/synchronization/clock information is received by a corresponding single buffer device and used to synchronize accesses to the memory device(s). Thus, multiple buffer integrated circuits on a module each receive information from the CPU using different wavelengths of light transmitted on the same waveguide.