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163 条记录 (耗时 0.041 秒)

    Multiple layer resist scheme implementing etch recipe particular to each layer
    111.
    发明授权
    Multiple layer resist scheme implementing etch recipe particular to each layer 有权
    多层抗蚀剂方案实现每层特有的蚀刻配方

    公开(公告)号：US07352064B2

    公开(公告)日：2008-04-01

    申请号：US10904323

    申请日：2004-11-04

    申请人： Nicholas C. M. Fuller ,  Timothy J. Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Hui Low

    发明人： Nicholas C. M. Fuller ,  Timothy J. Dalton ,  Raymond Joy ,  Yi-hsiung Lin ,  Chun Hui Low

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/4763

    CPC分类号： H01L21/76802 ,  H01L21/0332 ,  H01L21/31138 ,  H01L21/31144

    摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.

    摘要翻译： 公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。 该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层 层。 有机材料和无机材料之间的材料类型是交替的。 第三层被图案化为金属线和/或经由CD。 然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。 提供准确的CD形成和足够的抗蚀剂预算。

    Process for forming a damascene structure
    117.
    发明授权
    Process for forming a damascene structure 有权
    形成镶嵌结构的方法

    公开(公告)号：US06649531B2

    公开(公告)日：2003-11-18

    申请号：US09994340

    申请日：2001-11-26

    申请人： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

    发明人： William J. Cote ,  Timothy J. Dalton ,  Prakash Chimanlal Dev ,  Daniel C. Edelstein ,  Scott D. Halle ,  Gill Yong Lee ,  Arpan P. Mahorowala

    IPC分类号： H01L21302

    CPC分类号： H01L21/76808 ,  H01L21/31633

    摘要： A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

    摘要翻译： 用于形成镶嵌结构的方法包括将包括第一介电层和第二介电层的双层沉积到基板上，其中第一层具有高于第二层的介电常数，并且其中第二层选自低k 包含Si，C，O和H的介电材料。使用高选择性各向异性反应离子蚀刻，将多步镶嵌结构图案化成电介质双层。 使用等离子体灰化处理从基板去除光致抗蚀剂，聚合物和后蚀刻残留物，而不损坏下面的介电层。

    Interconnect structures containing stress adjustment cap layer
    118.
    发明授权
    Interconnect structures containing stress adjustment cap layer 有权
    互连结构包含应力调整盖层

    公开(公告)号：US06617690B1

    公开(公告)日：2003-09-09

    申请号：US10218292

    申请日：2002-08-14

    申请人： Stephen M. Gates ,  Timothy J. Dalton ,  John A. Fitzsimmons

    发明人： Stephen M. Gates ,  Timothy J. Dalton ,  John A. Fitzsimmons

    IPC分类号： H01L2940

    CPC分类号： H01L23/53295 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Novel interconnect structures possessing a relatively low internal stress and dielectric constant for use in semiconductor devices are provided herein. The novel interconnect structures comprise a first layer having a coefficient of thermal expansion greater than about 20 ppm and a first internal stress associated therewith, the first layer having a first set of metallic lines formed therein; a second layer having a coefficient of thermal expansion less than about 20 ppm and a second internal stress associated therewith, the second layer having a second set of metallic lines formed therein; and one or more stress adjustment cap layers formed between the first layer and the second layer, the cap layer(s) having a third internal stress to offset the first stress of the first layer and the second stress of the second layer and inducing a favorable relief of stress on the interconnect structure. Methods for making a semiconductor device having a substantially reduced internal stress are also provided.

    摘要翻译： 本文提供了具有用于半导体器件的相对低的内应力和介电常数的新型互连结构。 新颖的互连结构包括具有大于约20ppm的热膨胀系数的第一层和与其相关联的第一内部应力，第一层具有形成在其中的第一组金属线; 具有小于约20ppm的热膨胀系数的第二层和与其相关联的第二内应力，所述第二层在其中形成有第二组金属线; 以及形成在所述第一层和所述第二层之间的一个或多个应力调整盖层，所述盖层具有第三内应力以抵消所述第一层的第一应力和所述第二层的所述第二应力，并诱导有利的 减轻互连结构上的应力。 还提供了制造具有显着降低的内部应力的半导体器件的方法。

    On-chip decoupling capacitor with bottom hardmask
    120.
    发明授权
    On-chip decoupling capacitor with bottom hardmask 失效
    带底部硬掩模的片上去耦电容

    公开(公告)号：US06278147B1

    公开(公告)日：2001-08-21

    申请号：US09484359

    申请日：2000-01-18

    申请人： Timothy J. Dalton ,  Andrew P. Cowley ,  Peter A. Emmi ,  Erdem Kaltalioglu ,  Vincent J. McGahay

    发明人： Timothy J. Dalton ,  Andrew P. Cowley ,  Peter A. Emmi ,  Erdem Kaltalioglu ,  Vincent J. McGahay

    IPC分类号： H01L2976

    CPC分类号： H01L28/75 ,  H01L21/32136 ,  H01L21/32139

    摘要： An on-chip vertically stacked decoupling capacitor includes a hardmask film formed between the capacitor dielectric and the lower electrode. The manufacturing process used to form the capacitor takes advantage of the hardmask film and enables the capacitor to be formed over a low-k dielectric material. Attack of the underlying low-k dielectric material is suppressed during the etching and stripping processes used to form the capacitor, due to the presence of the hardmask. The low-k dielectric film provides for a reduced parasitic capacitance between adjacent conductive wires formed in the low-k dielectric material and therefore provides for increased levels of integration.

    摘要翻译： 片上垂直堆叠的去耦电容器包括形成在电容器电介质和下电极之间的硬掩模膜。 用于形成电容器的制造工艺利用了硬掩膜，并且使电容器能够在低k电介质材料上形成。 由于硬掩模的存在，在用于形成电容器的蚀刻和剥离工艺期间，抑制底层低k电介质材料的攻击。 低k电介质膜提供了在低k电介质材料中形成的相邻导线之间降低的寄生电容，因此提供了更高的集成度。