公开(公告)号：US20180174844A1

公开(公告)日：2018-06-21

申请号：US15898958

申请日：2018-02-19

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Isaac Lauer ,  Amlan Majumdar ,  Jeffrey W. Sleight

IPC: H01L21/265 ,  H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L29/786

CPC classification number: H01L21/2654 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78681

Abstract: Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual III-V semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first III-V semiconductor layer on an oxide; forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer; converting the first III-V semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second III-V semiconductor layer from at least one first active area selective to the first III-V semiconductor layer.

公开(公告)号：US09954063B2

公开(公告)日：2018-04-24

申请号：US15134190

申请日：2016-04-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/40 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

公开(公告)号：US09911592B2

公开(公告)日：2018-03-06

申请号：US15254394

申请日：2016-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

公开(公告)号：US09859375B2

公开(公告)日：2018-01-02

申请号：US15134155

申请日：2016-04-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/3065 ,  H01L29/04 ,  H01L29/40 ,  H01L29/786 ,  H01L21/306

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

公开(公告)号：US20170256612A1

公开(公告)日：2017-09-07

申请号：US15475917

申请日：2017-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Nicolas J. Loubet

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/423 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

公开(公告)号：US20170256610A1

公开(公告)日：2017-09-07

申请号：US15057439

申请日：2016-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Nicolas J. Loubet

IPC: H01L29/06 ,  H01L21/306 ,  H01L29/423 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

公开(公告)号：US09755017B1

公开(公告)日：2017-09-05

申请号：US15057439

申请日：2016-03-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael A. Guillorn ,  Isaac Lauer ,  Nicolas J. Loubet

IPC: H01L27/12 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/0673 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/32133 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78

Abstract: Nanosheet semiconductor devices and methods of forming the same include forming a first nanosheet stack in a first device region with layers of a first channel material and layers of a sacrificial material. A second nanosheet stack is formed in a second device region with layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material. The sacrificial material is etched away, but the liner protects the second channel material from the etch. Gate stacks are formed over and around the layers of first and second channel material to form respective first and second semiconductor devices in the first and second device regions.

公开(公告)号：US09754965B2

公开(公告)日：2017-09-05

申请号：US15352085

申请日：2016-11-15

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L27/1203 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/092 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/42388

Abstract: In one aspect, a method of forming a CMOS device includes forming nanowires suspended over a BOX, wherein a first/second one or more of the nanowires are suspended at a first/second suspension height over the BOX, and wherein the first suspension height is greater than the second suspension height; depositing a conformal gate dielectric on the BOX and around the nanowires wherein the conformal gate dielectric deposited on the BOX is i) in a non-contact position with the conformal gate dielectric deposited around the first one or more of the nanowires, and ii) is in direct physical contact with the conformal gate dielectric deposited around the second one or more of the nanowires such that the BOX serves as an oxygen source during growth of a conformal oxide layer at the interface between the conformal gate dielectric and the second one or more of the nanowires.

公开(公告)号：US20170236900A1

公开(公告)日：2017-08-17

申请号：US15045759

申请日：2016-02-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Field effect transistors and methods of forming the same include forming a stack of nanowires of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.

公开(公告)号：US20170221992A1

公开(公告)日：2017-08-03

申请号：US15493441

申请日：2017-04-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0676 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/41741 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/7827

Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A source and drain region is positioned at respective ends of the vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. The transistor includes a plurality of internal spacers, each formed between the gate stack and a respective source or drain region, with at least one pair of spacers being positioned above an uppermost channel layer.