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    DUAL EVENT COMMAND
    111.
    发明申请
    DUAL EVENT COMMAND 有权
    双重事件命令

    公开(公告)号：US20160225430A1

    公开(公告)日：2016-08-04

    申请号：US15093273

    申请日：2016-04-07

    Applicant: Micron Technology, Inc.

    Inventor： Joo S. Choi ,  Troy A. Manning ,  Brent Keeth

    IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/409

    CPC classification number: G11C11/4076 ,  G06F12/0207 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/408 ,  G11C11/409

    Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

    Abstract translation: 一种在时钟信号的时钟周期期间通过给定数量的一个或多个集成电路存储器件中的每一个中的命令和地址引脚来增加命令和寻址信号的传送速率的技术。 在一个示例实施例中，命令和地址信号在时钟信号的时钟周期的上升沿和下降沿上发送，以增加传输速率，并且基本上减少每个集成电路存储器件中所需的命令和地址引脚的数量。

    FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY
    115.
    发明申请
    FLEXIBLE MEMORY SYSTEM WITH A CONTROLLER AND A STACK OF MEMORY 有权
    具有控制器和存储器堆栈的灵活存储器系统

    公开(公告)号：US20140281204A1

    公开(公告)日：2014-09-18

    申请号：US13919503

    申请日：2013-06-17

    Applicant: Micron Technology, Inc.

    Inventor： Joe M. Jeddeloh ,  Brent Keeth

    IPC: G11C7/10

    CPC classification number: G11C5/066 ,  G11C5/025 ,  G11C5/14 ,  G11C7/10 ,  G11C11/4063 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: Embodiments of a system and method for providing a flexible memory system are generally described herein. In some embodiments, a substrate is provided, wherein a stack of memory is coupled to the substrate. The stack of memory includes a number of vaults. A controller is also coupled to the substrate and includes a number of vault interface blocks coupled to the number of vaults of the stack of memory, wherein the number of vault interface blocks is less than the number of vaults.

    Abstract translation: 本文一般地描述了用于提供柔性存储器系统的系统和方法的实施例。 在一些实施例中，提供了衬底，其中存储器堆叠耦合到衬底。 内存堆包括多个保管库。 控制器还耦合到基板并且包括耦合到存储器堆栈的多个保管库的多个保管库接口块，其中保管库接口块的数量小于保管库的数量。

    Memory device interface and method
    116.
    发明授权
    Memory device interface and method 有权

    公开(公告)号：US12277056B2

    公开(公告)日：2025-04-15

    申请号：US18215474

    申请日：2023-06-28

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

    IPC: G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

    Memory device interface and method
    119.
    发明授权
    Memory device interface and method 有权

    公开(公告)号：US12045500B2

    公开(公告)日：2024-07-23

    申请号：US18138527

    申请日：2023-04-24

    Applicant: Micron Technology, Inc.

    Inventor： Brent Keeth

    IPC: G06F3/06 ,  G11C5/04 ,  G11C7/10

    CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C5/04 ,  G11C7/1006

    Abstract: Apparatus and methods are disclosed, including memory devices and systems. In an example, a memory module can include a first stack of at least eight memory die including four pairs of memory die, each pair of the four pairs of memory die associated with an individual memory rank of four memory ranks of the memory module, a memory controller configured to receive memory access commands and to access memory locations of the first stack, and a substrate configured to route connections between external terminations of the memory module and the memory controller.

    TECHNIQUES FOR COUPLED HOST AND MEMORY DIES
    120.
    发明公开
    TECHNIQUES FOR COUPLED HOST AND MEMORY DIES 审中-公开

    公开(公告)号：US20240176523A1

    公开(公告)日：2024-05-30

    申请号：US18516734

    申请日：2023-11-21

    Applicant: Micron Technology, Inc.

    Inventor： James Brian Johnson ,  Brent Keeth ,  Kunal R. Parekh ,  Eiichi Nakano ,  Amy Rae Griffin ,  Ameen D. Akel

    IPC: G06F3/06 ,  G06F1/06

    CPC classification number: G06F3/064 ,  G06F1/06 ,  G06F3/061 ,  G06F3/0683

    Abstract: Methods, systems, and devices for techniques for coupled host and memory dies are described. For example, to distribute memory access circuitry among multiple semiconductor dies of a stack, a first die may include a set of one or more memory arrays and a first portion of the circuitry configured to access the set of memory arrays, and a second die may include a second portion of the circuitry configured to access the set of memory arrays. The first portion and the second portion of the circuitry configured to access a set of memory arrays may be communicatively coupled between the dies using various interconnection techniques, such as a fusion of conductive contacts of the respective memory dies. In some examples, the second die may also include the host itself (e.g., a host processor).

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