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公开(公告)号：US20180294222A1
公开(公告)日：2018-10-11
申请号：US16009429
申请日：2018-06-15
Applicant: Renesas Electronics Corporation
Inventor： Teruhiro KUWAJIMA , Akira MATSUMOTO , Yasutaka NAKASHIBA , Takashi IWADARE
IPC: H01L23/522
CPC classification number: H01L23/5227 , H01L23/4952 , H01L23/49551 , H01L2224/05554 , H01L2224/4813 , H01L2224/49175
Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
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公开(公告)号：US20180277518A1
公开(公告)日：2018-09-27
申请号：US15861231
申请日：2018-01-03
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuya IIDA , Yasutaka NAKASHIBA , Nobuya KOIKE
IPC: H01L25/065 , H01L23/528 , H01L23/00 , H01L23/522 , H01L23/532 , H01L23/31 , H01L23/544 , H01L25/00 , H01L21/78 , H01L21/56 , H01L21/02 , H01L23/495
CPC classification number: H01L25/0657 , H01L21/0214 , H01L21/0217 , H01L21/56 , H01L21/78 , H01L23/3107 , H01L23/3114 , H01L23/49541 , H01L23/49575 , H01L23/5227 , H01L23/528 , H01L23/5329 , H01L23/544 , H01L24/05 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/85 , H01L24/92 , H01L25/50 , H01L2223/54426 , H01L2224/05554 , H01L2224/32145 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48463 , H01L2224/73215 , H01L2224/73265 , H01L2224/83139 , H01L2224/8385 , H01L2224/92147 , H01L2224/92247 , H01L2225/0651 , H01L2225/06531 , H01L2225/06562 , H01L2225/06593 , H01L2924/13055 , H01L2924/181 , H01L2924/00014 , H01L2924/00012 , H01L2924/00
Abstract: An improvement is achieved in the reliability of a semiconductor device. A first semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a first insulating film formed over the insulating film. A second semiconductor chip includes a semiconductor substrate, a wiring structure formed over the semiconductor substrate, an insulating film formed over the wiring structure, and a second insulating film formed over the insulating film. The first insulating film forms an uppermost layer of the first semiconductor chip. The second insulating film forms an uppermost layer of the second semiconductor chip. Each of the first and second insulating films is made of a photosensitive resin film having an adhesive property. The first and second semiconductor chips are stacked such that the first insulating film of the first semiconductor chip and the second insulating film of the second semiconductor chip are in contact with each other.
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公开(公告)号：US20180246276A1
公开(公告)日：2018-08-30
申请号：US15961435
申请日：2018-04-24
Applicant: Renesas Electronics Corporation
Inventor： Yasutaka NAKASHIBA , Shinichi WATANUKI
CPC classification number: G02B6/122 , G02B6/136 , G02B6/34 , G02B2006/12038 , G02B2006/12061 , G02B2006/12097 , G02B2006/12107 , G02F1/025
Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.
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公开(公告)号：US20180047680A1
公开(公告)日：2018-02-15
申请号：US15635425
申请日：2017-06-28
Applicant: Renesas Electronics Corporation
Inventor： Shinichi UCHIDA , Yasutaka NAKASHIBA
IPC: H01L23/58 , H01L23/535 , H01L23/528 , H01L29/10 , H01L21/84 , H01L23/00 , H01L29/06 , H01L27/12 , H01L23/522
CPC classification number: H01L23/585 , H01L21/84 , H01L23/5226 , H01L23/528 , H01L23/535 , H01L23/564 , H01L27/1203 , H01L27/1207 , H01L29/0649 , H01L29/1095
Abstract: A semiconductor device includes an annular seal ring formed in a seal ring region surrounding a circuit forming region. The seal ring includes a BOX layer, an n-type semiconductor layer, and an annular electrode portion comprised of multiple layers of wirings. The electrode portion is electrically connected with the n-type semiconductor layer through a plug electrode.
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公开(公告)号：US20180007298A1
公开(公告)日：2018-01-04
申请号：US15639231
申请日：2017-06-30
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Tetsuya IIDA , Yasutaka NAKASHIBA
IPC: H04N5/378 , H04N5/376 , H04N5/341 , H04N5/3745
CPC classification number: H04N5/378 , H04N5/341 , H04N5/3745 , H04N5/3765
Abstract: To provide an imaging device capable of reducing the amount of data with a simple method. An imaging device includes: a plurality of sensor elements which is arranged in a matrix shape and each of which generates a photoelectric conversion voltage in accordance with an input light level; and a read circuit which is coupled to bit lines provided while being associated with respective columns of the sensor elements, and amplifies and reads the photoelectric conversion voltages generated in the sensor elements by being exposed at predetermined timing. The read circuit outputs differential data of the read photoelectric conversion voltages generated in the respective sensor elements that are adjacent to each other in the same row or column.
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Patent Agency Ranking
公开(公告)号：US20170229510A1
公开(公告)日：2017-08-10
申请号：US15372775
申请日：2016-12-08
Applicant: Renesas Electronics Corporation
Inventor： Tetsuya IIDA , Yasutaka NAKASHIBA
IPC: H01L27/146
CPC classification number: H01L27/14643 , H01L27/14607 , H01L27/1461 , H01L27/14614
Abstract: A solid-state image sensing device capable of suppressing a dark current and transfer failure during a global shutter operation is provided. The solid-state image sensing device according to one embodiment includes: a semiconductor substrate having a main surface and a back surface being on the opposite side of the main surface; a well region arranged in contact with the main surface in the semiconductor substrate; a photoelectric conversion region arranged in contact with the main surface in the well region; a charge holding region arranged in contact with the main surface in the well region; a floating diffusion region arranged in contact with the main surface in the well region; a first transfer gate so formed as to face the well region and the charge holding region; and a second transfer gate so formed as to face the well region.
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公开(公告)号：US20170077013A1
公开(公告)日：2017-03-16
申请号：US15341332
申请日：2016-11-02
Applicant: Renesas Electronics Corporation
Inventor： Akira MATSUMOTO , Yoshinao MIURA , Yasutaka NAKASHIBA
IPC: H01L23/495 , H01L23/00 , H01L29/778 , H01L29/20 , H01L29/205
CPC classification number: H01L23/49562 , H01L23/4824 , H01L23/485 , H01L23/492 , H01L23/49503 , H01L23/4952 , H01L23/49548 , H01L23/49575 , H01L23/50 , H01L23/528 , H01L23/5283 , H01L24/06 , H01L24/45 , H01L24/48 , H01L24/49 , H01L27/0203 , H01L27/0605 , H01L27/088 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/41758 , H01L29/4236 , H01L29/7786 , H01L29/7787 , H01L29/78 , H01L2224/04042 , H01L2224/05553 , H01L2224/0603 , H01L2224/06051 , H01L2224/45014 , H01L2224/451 , H01L2224/4805 , H01L2224/4813 , H01L2224/48177 , H01L2224/48247 , H01L2224/49113 , H01L2924/00014 , H01L2924/0002 , H01L2924/1033 , H01L2924/10344 , H01L2924/13064 , H01L2924/30101 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
Abstract: Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side in a first direction, each of which has a plurality of transistors. The gate electrodes of the transistors extend in the first direction. First source wiring extends between first transistor unit and second transistor unit, and first drain wiring extends between the second transistor unit and third transistor unit. Second drain wiring extends on the side of the first transistor unit opposite to the side where the first source wiring extends, and second source wiring extends on the side of the third transistor unit opposite to the side where the second drain wiring extends.
Abstract translation: 公开了一种半导体器件，其中由布线产生的电阻分量减小。 多个晶体管单元沿第一方向并排布置，每个晶体管单元具有多个晶体管。 晶体管的栅电极沿第一方向延伸。 第一源极布线在第一晶体管单元和第二晶体管单元之间延伸，并且第一漏极布线在第二晶体管单元和第三晶体管单元之间延伸。 第二漏极布线在第一晶体管单元的与第一源极布线延伸的一侧相反的一侧延伸，并且第二源极布线在与第二漏极布线延伸的一侧相反的一侧延伸。
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公开(公告)号：US20170062332A1
公开(公告)日：2017-03-02
申请号：US15186734
申请日：2016-06-20
Applicant: Renesas Electronics Corporation
Inventor： Teruhiro KUWAJIMA , Akira MATSUMOTO , Yasutaka NAKASHIBA , Takashi IWADARE
IPC: H01L23/522
CPC classification number: H01L23/5227 , H01L23/4952 , H01L23/49551 , H01L2224/05554 , H01L2224/4813 , H01L2224/49175
Abstract: A SOP has a semiconductor chip. The chip includes a pair of a lower layer coil and an upper layer coil laminated through an interlayer insulating film formed therebetween, a first circuit unit electrically coupled to the upper layer coil, and a plurality of electrode pads. Further, it has a wire for electrically coupling the upper layer coil and the first circuit unit, a plurality of inner leads and outer leads arranged around the semiconductor chip, a plurality of wires for electrically coupling the electrode pads of the semiconductor chip and the inner leads, and a resin made sealing member for covering the semiconductor chip. The wire extends along the extending direction of the wires.
Abstract translation: SOP具有半导体芯片。 芯片包括一对下层线圈和层叠在其间形成的层间绝缘膜的上层线圈，电耦合到上层线圈的第一电路单元和多个电极焊盘。 此外，它具有用于电耦合上层线圈和第一电路单元的导线，布置在半导体芯片周围的多个内部引线和外部引线，用于电连接半导体芯片的电极焊盘和内部 引线和用于覆盖半导体芯片的树脂制密封构件。 电线沿电线的延伸方向延伸。
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公开(公告)号：US20170031094A1
公开(公告)日：2017-02-02
申请号：US15186610
申请日：2016-06-20
Applicant: Renesas Electronics Corporation
Inventor： Yasutaka NAKASHIBA , Shinichi WATANUKI
CPC classification number: G02B6/122 , G02B6/136 , G02B6/34 , G02B2006/12038 , G02B2006/12061 , G02B2006/12097 , G02B2006/12107 , G02F1/025
Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.
Abstract translation: 包括光波导和p型半导体部分的半导体器件被配置如下。 光波导包括：形成在绝缘层上的第一半导体层; 形成在所述第一半导体层上的绝缘层; 以及形成在所述绝缘层上的第二半导体层。 p型半导体部分包括第一半导体层。 p型半导体部的膜厚小于光波导的膜厚。 通过在第一半导体层和第二半导体层之间形成绝缘层，便于光波导和p型半导体部分的膜厚的控制。 具体地说，当在形成p型半导体部分的步骤中通过蚀刻除去不必要的第二半导体层时，作为下层的绝缘层用作蚀刻停止层，p型半导体部分的膜厚可以 容易调整。
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公开(公告)号：US20160334573A1
公开(公告)日：2016-11-17
申请号：US15152117
申请日：2016-05-11
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Hiroyuki KUNISHIMA , Yasutaka NAKASHIBA , Masaru WAKABAYASHI , Shinichi WATANUKI
IPC: G02B6/122 , G02B6/28 , H01L23/522 , G02F1/025 , H01L23/528 , H01L23/532
CPC classification number: G02F1/025 , G02B6/125 , G02B6/132 , G02B6/2852 , G02B2006/12061 , G02B2006/12142 , G02B2006/12147 , G02F2201/08 , H01L23/53214 , H01L23/53228 , H01L2224/05
Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.
Abstract translation: 在具有第一反射率的光学定向耦合器和第一层布线之间形成具有比第一反射率低的第二反射率（50％或更低）的低反射率膜。 因此，即使当第一层布线形成在光学定向耦合器上方时，由第一层布线反射的光对通过光学定向耦合器的第一光波导和第二光波导传播的光信号的影响可以 减少 因此，第一层布线可以布置在光学定向耦合器的上方，并且第一层布线的布局的限制被放宽。
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