公开(公告)号：US20160315175A1

公开(公告)日：2016-10-27

申请号：US14984445

申请日：2015-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/324 ,  H01L21/768 ,  H01L21/3065

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/5256 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/785

Abstract: An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.

公开(公告)号：US09472621B1

公开(公告)日：2016-10-18

申请号：US14955738

申请日：2015-12-01

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Joshua M. Rubin

IPC: H01L21/84 ,  H01L31/18 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/311 ,  H01L21/324 ,  H01L29/66

CPC classification number: H01L29/1054 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/0254 ,  H01L21/02614 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32105 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/84 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of forming CMOS structures with selective tensile strained NFET fins and relaxed PFET fins includes performing a first, partial fin etch on a tensile strained silicon layer of a semiconductor substrate; selectively oxidizing bottom surfaces of the tensile strained silicon layer in a PFET region of the semiconductor substrate, thereby causing PFET silicon fins defined in the PFET region to become relaxed; and performing a second fin etch to define NFET silicon fins in an NFET region of the semiconductor substrate, wherein the NFET silicon fins remain tensile strained.

Abstract translation: 一种形成具有选择性拉伸应变NFET鳍片和弛豫PFET鳍片的CMOS结构的方法包括在半导体衬底的拉伸应变硅层上执行第一部分鳍片蚀刻; 选择性地氧化半导体衬底的PFET区域中的拉伸应变硅层的底表面，从而使在PFET区域中限定的PFET硅翅片变得松弛; 以及执行第二鳍蚀刻以在所述半导体衬底的NFET区域中限定NFET硅散热片，其中所述NFET硅散热片保持拉伸应变。

公开(公告)号：US20160225789A1

公开(公告)日：2016-08-04

申请号：US14609574

申请日：2015-01-30

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/306 ,  H01L29/78 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming replacement fins in a complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor device (nFET) and a CMOS device are described. The method includes forming strained silicon (Si) fins from a strained silicon-on-insulator (SSOI) layer in both an nFET region and a pFET region, forming insulating layers over the strained Si fins, and forming trenches within the insulating layers to expose the strained Si fins in the pFET region only. The method also includes etching the strained Si fins in the pFET region to expose a buried oxide (BOX) layer of the SSOI layer, etching the exposed portions of the BOX layer to expose a bulk substrate, epitaxially growing a Si portion of pFET replacement fins from the bulk substrate, and epitaxially growing silicon germanium (SiGe) portions of the pFET replacement fins on the Si portion of the pFET replacement fins.

公开(公告)号：US09406746B2

公开(公告)日：2016-08-02

申请号：US14184229

申请日：2014-02-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/31122 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

Abstract translation: 一种形成半导体器件的方法，包括在鳍结构的沟道部分上形成牺牲栅极结构，其中牺牲栅极结构的侧壁与鳍结构的沟道部分的上表面的交点处的角度为 钝。 外延源极和漏极区结构形成在鳍结构的源极区域和漏极区域部分上。 在牺牲栅极结构的侧壁上形成至少一种电介质材料。 可以去除牺牲栅极结构以为鳍结构的通道部分提供开口。 在开口中形成功能门结构。 由功能门结构的侧壁与翅片结构的通道部分的上表面的交点限定的至少一个角度是钝的。

公开(公告)号：US09331073B2

公开(公告)日：2016-05-03

申请号：US14497380

申请日：2014-09-26

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Hong He ,  Seth L. Knupp ,  Raghavasimhan Sreenivasan ,  Sean Teehan ,  Allan W. Upham ,  Chih-Chao Yang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/04 ,  H01L29/12 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/122 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth.

Abstract translation: 在{100}晶体取向翅片上形成具有共形外延阱的量子阱的方法。 该方法可以包括：在{100}晶体取向的基底中形成翅片; 使用外延生长在翅片上形成保形阱; 并使用外延生长在保形阱上形成共形势垒。

公开(公告)号：US20160118302A1

公开(公告)日：2016-04-28

申请号：US14985711

申请日：2015-12-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L21/033 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

公开(公告)号：US09324830B2

公开(公告)日：2016-04-26

申请号：US14227345

申请日：2014-03-27

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/283 ,  H01L29/165

CPC classification number: H01L23/535 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: Self-aligned contacts of a semiconductor device are fabricated by forming a metal gate structure on a portion of a semiconductor layer of a substrate. The metal gate structure contacts inner sidewalls of a gate spacer. A second sacrificial epitaxial layer is formed on a first sacrificial epitaxial layer. The first sacrificial epitaxial layer is adjacent to the gate spacer and is formed on source/drain regions of the semiconductor layer. The first and second sacrificial epitaxial layers are recessed. The recessing exposes at least a portion of the source/drain regions. A first dielectric layer is formed on the exposed portions of the source/drain regions, and over the gate spacer and metal gate structure. At least one cavity within the first dielectric layer is formed above at least one of the exposed portions of source/drain regions. At least one metal contact is formed within the at least one cavity.

Abstract translation: 通过在衬底的半导体层的一部分上形成金属栅极结构来制造半导体器件的自对准接触。 金属栅极结构接触栅极间隔物的内侧壁。 在第一牺牲外延层上形成第二牺牲外延层。 第一牺牲外延层与栅极间隔物相邻并形成在半导体层的源/漏区上。 第一和第二牺牲外延层是凹进的。 凹陷暴露出源极/漏极区域的至少一部分。 第一电介质层形成在源极/漏极区域的暴露部分上并且在栅极间隔物和金属栅极结构之上。 在源极/漏极区域的至少一个暴露部分之上形成第一介电层内的至少一个空腔。 在至少一个空腔内形成至少一个金属接触件。

公开(公告)号：US20160093613A1

公开(公告)日：2016-03-31

申请号：US14497380

申请日：2014-09-26

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  James J. Demarest ,  Hong He ,  Seth L. Knupp ,  Raghavasimhan Sreenivasan ,  Sean Teehan ,  Allan W. Upham ,  Chih-Chao Yang

IPC: H01L27/088 ,  H01L29/04 ,  H01L29/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/122 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a quantum well having a conformal epitaxial well on a {100} crystallographic orientated fin. The method may include: forming fins in a {100} crystallographic oriented substrate; forming a conformal well on the fins using epitaxial growth; and forming a conformal barrier on the conformal well using epitaxial growth.

Abstract translation: 在{100}晶体取向翅片上形成具有共形外延阱的量子阱的方法。 该方法可以包括：在{100}晶体取向的基底中形成翅片; 使用外延生长在翅片上形成保形阱; 并使用外延生长在保形阱上形成共形势垒。

公开(公告)号：US09252014B2

公开(公告)日：2016-02-02

申请号：US14017443

申请日：2013-09-04

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/02647 ,  H01L21/02041 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a semiconductor device includes forming an insulator layer over a substrate; opening a trench in the insulator layer so as to expose one or more semiconductor structures formed on the substrate; forming a protective layer on sidewalls of the trench; subjecting the substrate to a precleaning operation in preparation for epitaxial semiconductor formation, wherein the protective layer prevents expansion of the sidewalls of the trench as a result of the precleaning operation; and forming epitaxial semiconductor material within the trench and over the exposed one or more semiconductor structures.

公开(公告)号：US20160027776A1

公开(公告)日：2016-01-28

申请号：US14877186

申请日：2015-10-07

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L27/088 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/3085 ,  H01L21/3088 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a fin-based field-effect transistor device includes forming one or more first fins comprising silicon on a substrate, forming epitaxial layers on sides of the one or more first fins, and removing the one or more first fins to form a plurality of second fins.