公开(公告)号：US20210167067A1

公开(公告)日：2021-06-03

申请号：US17061920

申请日：2020-10-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Hiroyuki MIYAKE ,  Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/13 ,  H01L27/115 ,  H01L29/786

Abstract: It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

公开(公告)号：US20210091083A1

公开(公告)日：2021-03-25

申请号：US16613478

申请日：2018-05-07

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi KATO

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor device capable of retaining data for a long period is provided. The semiconductor device includes a first memory cell and a second memory cell. The first memory cell includes a first transistor. The second memory cell includes a second transistor. The threshold voltage of the second transistor is higher than the threshold voltage of the first transistor. The first transistor includes a first metal oxide. The second transistor includes a second metal oxide. Each of the first metal oxide and the second metal oxide includes a channel formation region. Each of the first metal oxide and the second metal oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn. The atomic ratio of the element M to In in the second metal oxide is greater than that in the first metal oxide.

公开(公告)号：US20210081023A1

公开(公告)日：2021-03-18

申请号：US17104460

申请日：2020-11-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei MAEDA ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: G06F1/3234 ,  G11C16/30 ,  G11C14/00 ,  G11C5/14

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US20210027828A1

公开(公告)日：2021-01-28

申请号：US17041037

申请日：2019-03-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Takahiko ISHIZU ,  Tatsuya ONUKI

IPC: G11C11/408 ,  H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786

Abstract: A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

公开(公告)号：US20200279589A1

公开(公告)日：2020-09-03

申请号：US16643755

申请日：2018-09-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G11C7/06 ,  G11C14/00

Abstract: To provide a novel semiconductor device.The semiconductor device includes cell arrays and peripheral circuits; the cell arrays include memory cells; the peripheral circuits includes a first driver circuit, a second driver circuit, a first amplifier circuit, a second amplifier circuit, a third amplifier circuit, and a fourth amplifier circuit; the first driver circuit and the second driver circuit have a function of supplying a selection signal to the cell array; the first amplifier circuit and the second amplifier circuit have a function of amplifying a potential input from the cell array; the third amplifier circuit and the fourth amplifier circuit have a function of amplifying a potential input from the first amplifier circuit or the second amplifier circuit; the first driver circuit, the second driver circuit, the first amplifier circuit, the second amplifier circuit, the third amplifier circuit, and the fourth amplifier circuit include a region overlapping with the cell array; and the memory cells include a metal oxide in a channel formation region.

公开(公告)号：US20190377401A1

公开(公告)日：2019-12-12

申请号：US16476642

申请日：2018-01-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei MAEDA ,  Shuhei NAGATSUKA ,  Tatsuya ONUKI ,  Kiyoshi KATO

IPC: G06F1/3234 ,  G11C5/14 ,  G11C16/30 ,  G11C14/00

Abstract: To reduce the area of a memory cell having a backup function. A storage device includes a cell array, and a row circuit and a column circuit that drive the cell array. The cell array includes a first power supply line, a second power supply line, a word line, a pair of bit lines, a memory cell, and a backup circuit. The cell array is located in a power domain where power gating can be performed. In the power gating sequence of the cell array, data in the memory cell is backed up to the backup circuit. The backup circuit is stacked over a region where the memory cell is formed. A plurality of wiring layers are provided between the backup circuit and the memory cell. The first power supply line, the second power supply line, the word line, and the pair of bit lines are located in different wiring layers.

公开(公告)号：US20190222209A1

公开(公告)日：2019-07-18

申请号：US16362777

申请日：2019-03-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi KATO ,  Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Takanori MATSUZAKI

IPC: H03K5/24 ,  H01L49/02 ,  H01L27/146 ,  H01L27/108 ,  H01L23/498 ,  G11C5/14 ,  H01L21/78 ,  H01L27/00

CPC classification number: H03K5/2481 ,  G11C5/144 ,  G11C5/145 ,  H01L21/78 ,  H01L23/49844 ,  H01L27/00 ,  H01L27/10805 ,  H01L27/14687 ,  H01L28/00

Abstract: Provided is a semiconductor device that can directly compare two negative potentials. The semiconductor device includes a first to a third transistor and a load and is configured to compare a first negative potential and a second negative potential. The first negative potential and the second negative potential are input to a gate of the first transistor and a gate of the second transistor, respectively. Each drain of the first transistor and the second transistor is electrically connected to the load. The third transistor serves as a current source. The first transistor and the second transistor each include a backgate. A positive potential is input to the backgates.

公开(公告)号：US20180254291A1

公开(公告)日：2018-09-06

申请号：US15966231

申请日：2018-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Kiyoshi KATO ,  Satoru OKAMOTO

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/66 ,  H01L29/786 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/105 ,  H01L29/24

CPC classification number: H01L27/1207 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02178 ,  H01L21/02183 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/76813 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/8258 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/0629 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/1225 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869

Abstract: A highly reliable semiconductor device suitable for miniaturization and high integration is provided. The semiconductor device includes a first insulator; a transistor over the first insulator; a second insulator over the transistor; a first conductor embedded in an opening in the second insulator; a barrier layer over the first conductor; a third insulator over the second insulator and over the barrier layer; and a second conductor over the third insulator. The first insulator, the third insulator, and the barrier layer have a barrier property against oxygen and hydrogen. The second insulator includes an excess-oxygen region. The transistor includes an oxide semiconductor. The barrier layer, the third insulator, and the second conductor function as a capacitor.

公开(公告)号：US20180005668A1

公开(公告)日：2018-01-04

申请号：US15626595

申请日：2017-06-19

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yutaka SHIONOIRI ,  Tomoaki ATSUMI ,  Kiyoshi KATO ,  Takanori MATSUZAKI

IPC: G11C5/06 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24

CPC classification number: G11C5/06 ,  G11C5/025 ,  G11C5/063 ,  G11C11/403 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4097 ,  H01L21/8258 ,  H01L27/0222 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/24 ,  H01L29/7869

Abstract: To provide a semiconductor device with a high output voltage. A gate of a first transistor is electrically connected to a first terminal through a first capacitor. A gate of a second transistor is electrically connected to a second terminal through a second capacitor. One of a source and a drain of a third transistor is electrically connected to the gate of the first transistor through a third capacitor. One of a source and a drain of a fourth transistor is electrically connected to the gate of the second transistor through a fourth capacitor. The other of the source and the drain of the third transistor and the other of the source and the drain of the fourth transistor are electrically connected to a high potential power source. A third terminal is electrically connected to one of a source and a drain of the second transistor.

公开(公告)号：US20170301380A1

公开(公告)日：2017-10-19

申请号：US15635550

申请日：2017-06-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: G11C7/10 ,  H01L27/12 ,  H01L27/06 ,  H01L23/528 ,  G11C8/08 ,  G11C7/22 ,  G11C7/18 ,  H01L29/786 ,  G11C7/12

CPC classification number: G11C7/10 ,  G11C5/06 ,  G11C5/147 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/08 ,  G11C11/24 ,  G11C11/4097 ,  G11C16/0433 ,  G11C16/28 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02631 ,  H01L23/528 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/22 ,  H01L29/24 ,  H01L29/26 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of the present invention is to provide a semiconductor device combining transistors integrating on a same substrate transistors including an oxide semiconductor in their channel formation region and transistors including non-oxide semiconductor in their channel formation region. An application of the present invention is to realize substantially non-volatile semiconductor memories which do not require specific erasing operation and do not suffer from damages due to repeated writing operation. Furthermore, the semiconductor device is well adapted to store multivalued data. Manufacturing methods, application circuits and driving/reading methods are explained in details in the description.