公开(公告)号：US06951978B1

公开(公告)日：2005-10-04

申请号：US10739047

申请日：2003-12-19

Applicant: Richard S. Norman

Inventor： Richard S. Norman

IPC: H01B11/00 ,  H05K1/02

CPC classification number: H05K1/0228 ,  H05K2201/09245 ,  H05K2201/09263

Abstract: A conductive fabric including a plurality of conductive elements defining an alternating sequence of segments and cross-over regions. Within each of the segments, the conductive elements are arranged substantially in parallel; within each of the cross-over regions located between two adjacent segments, the conductive elements are permuted so as to allow the position occupied by at least one of the conductive elements to be different in each of the two adjacent segments. Between a pair of reference segments, each of the conductive elements experience coupling with respect to a subset of said conductive elements other than itself, the coupling experienced by each of the conductive elements being substantially identical.

Abstract translation: 导电织物，其包括限定段和交叉区域的交替序列的多个导电元件。 在每个段内，导电元件基本上平行布置; 在位于两个相邻段之间的每个交叉区域内，导电元件被置换，以允许至少一个导电元件占据的位置在两个相邻段中的每一个中不同。 在一对参考段之间，每个导电元件相对于除本身之外的所述导电元件的子集经历耦合，由每个导电元件经历的耦合基本相同。

公开(公告)号：US20040184247A1

公开(公告)日：2004-09-23

申请号：US10800696

申请日：2004-03-16

Inventor： Luc Adriaenssens ,  Amid Hashim ,  Troy Long

IPC: H01R024/00 ,  H05K001/16

CPC classification number: H01R13/6466 ,  H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K3/4688 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09672 ,  H05K2201/10189

Abstract: A connector is provided for simultaneously improving both the NEXT high frequency performance when low crosstalk plugs are used and the NEXT low frequency performance when high crosstalk plugs are used. The connector includes PCB substrates made of materials having different dielectric frequency characteristics.

Abstract translation: 提供连接器，用于当使用低串扰插头时同时提高NEXT高频性能，并且当使用高串扰插头时NEXT低频性能。 连接器包括由具有不同介电频率特性的材料制成的PCB衬底。

公开(公告)号：US20040129453A1

公开(公告)日：2004-07-08

申请号：US10337949

申请日：2003-01-07

Inventor： David W. Boggs ,  Daryl Sato ,  John Dungan

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K1/112 ,  H05K3/4076 ,  H05K3/421 ,  H05K2201/09245 ,  H05K2201/09472 ,  H05K2201/09509

Abstract: Embodiments of substrate in accordance with the present invention provide interconnect cavities for direct interconnection between SMT components and internal conductive inner layers, as well as surface outer layers. Interconnect cavities eliminate the need for through hole vias and require less substrate surface area and internal volume. Each interconnect cavity comprises a cavity extending from the substrate surface to an adjacent internal conductive inner layer directly beneath the cavity. The cavity extends through a conductive outer layer on the substrate surface. The cavity has a conductive liner interconnected with the outer layer and the inner layer forming a cup-shaped conductive depression interconnecting the outer layer with the inner layer.

Abstract translation: 根据本发明的衬底的实施例提供用于SMT部件和内部导电内层之间以及表面外层的直接互连的互连腔。 互连腔消除了对通孔的需要，并且需要较少的衬底表面积和内部体积。 每个互连腔包括从衬底表面延伸到空腔正下方的相邻内部导电内层的空腔。 空腔延伸穿过衬底表面上的导电外层。 空腔具有与外层互连的导电衬垫，内层形成将外层与内层互连的杯形导电凹部。

公开(公告)号：US20020081894A1

公开(公告)日：2002-06-27

申请号：US09745457

申请日：2000-12-21

Inventor： Robert M. Fuerst ,  Prashant Joshi ,  Yves LePottier ,  David A. Pfaffinger

IPC: H01R012/24

CPC classification number: H01R12/613 ,  H05K1/0289 ,  H05K1/118 ,  H05K3/281 ,  H05K3/361 ,  H05K3/363 ,  H05K2201/09245

Abstract: A system and method are provided for interconnecting the generally parallel conductors of a pair of flat circuits out of sequential order relative to each other. The system includes a pair of flat circuits each having a plurality of generally parallel conductors covered by a dielectric film. A pattern of windows are formed in the film of each circuit to expose the conductors at different locations longitudinally thereof. The patterns of windows of the two circuits are coincident with each other when the flat circuits are overlapped with each other and with the circuits oriented so that the conductors of the circuits are at angles relative to each other. The conductors of the respective circuits are electrically connected through the windows.

Abstract translation: 提供了一种系统和方法，用于使一对扁平电路的大致平行的导体相对于彼此以顺序的顺序相互连接。 该系统包括一对扁平电路，每个平面电路具有由介电膜覆盖的多个大致平行的导体。 在每个电路的膜中形成窗口图案，以在其纵向的不同位置露出导体。 当平坦电路彼此重叠并且电路定向使得电路的导体相对于彼此成角度时，两个电路的窗口的图案彼此一致。 各个电路的导体通过窗户电连接。

公开(公告)号：US20020076903A1

公开(公告)日：2002-06-20

申请号：US10007703

申请日：2001-12-10

Inventor： Koji Kondo ,  Tetsuaki Kamiya ,  Toshikazu Harada ,  Ryuichi Onoda ,  Yasutaka Kamiya ,  Gentaro Masuda ,  Yoshitaro Yazaki ,  Tomohiro Yokochi

IPC: H01L021/30 ,  H01L021/46 ,  H01L021/4763

CPC classification number: H05K3/4638 ,  H05K3/0035 ,  H05K3/281 ,  H05K3/4069 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0129 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09245 ,  H05K2201/096 ,  H05K2201/09854 ,  H05K2203/063 ,  H05K2203/065 ,  H05K2203/1476 ,  H05K2203/1572 ,  Y10T156/1064

Abstract: Single-sided conductor patterned films are prepared, each of which has a conductor pattern formed only one side of a resin film and via hole filled with conductive paste. A single-sided conductor patterned film which has a conductor pattern formed only one side of a resin film and an opening formed in the resin film so as to expose an electrode is laminated on the single-sided conductor patterned films. Moreover, a cover layer with an opening to expose an electrode is laminated on a bottom surface of the single-sided conductor patterned films to form a laminate. Then, by pressing while heating the laminate, a multilayer substrate having the electrodes at both sides thereof can be produced.

Abstract translation: 制备单面导体图案化膜，其每一个具有只形成树脂膜的一侧的导体图案和填充有导电浆料的通孔。 在单面导体图案化膜上层叠单面导体图案膜，其具有仅形成树脂膜的一侧的导体图案和形成在树脂膜中以露出电极的开口。 此外，在单面导体图案化膜的底面上层叠具有露出电极的开口的覆盖层，以形成层压体。 然后，通过在加热层叠体的同时按压，可以制造在其两侧具有电极的多层基板。

公开(公告)号：US06351351B1

公开(公告)日：2002-02-26

申请号：US09396896

申请日：1999-09-15

Applicant: Satoru Takasugi

Inventor： Satoru Takasugi

IPC: G11B560

CPC classification number: G11B5/486 ,  H05K3/244 ,  H05K3/28 ,  H05K3/363 ,  H05K2201/0367 ,  H05K2201/09245 ,  H05K2201/10681

Abstract: The present invention provides an improved magnetic head suspension including a flexure with a flexure wiring structure therein, a load beam constituting a suspension in cooperation with the flexure, and a relay FPC with a flexure wiring structure therein for connection between the flexure and an external wiring structure. A flexure signal line portion has a characteristic impedance matching with that of an FPC signal line portion. A connection portion of the flexure wiring structure has a width substantially equal to that of the FPC signal line portion, and has a length determined by multiplying a positional error in joining between the flexure and the FPC by two and adding the result to the width of the connection portion of the FPC wiring structure. The connection portion of the FPC wiring structure has a width substantially equal to that of the flexure wiring structure, and has a length determined by multiplying the positional error by two and adding the result to the width of the connection portion of the flexure wiring structure. The connection portion of the flexure wiring structure crosses the connection portion of the FPC wiring structure at right angle and is connected thereto.

Abstract translation: 本发明提供了一种改进的磁头悬架，其包括其中具有弯曲布线结构的挠曲件，构成与挠曲件协作的悬架的负载梁，以及用于在挠曲件和外部布线之间连接的挠性布线结构的继电器FPC 结构体。 弯曲信号线部分具有与FPC信号线部分的特性阻抗匹配的特性阻抗。 柔性布线结构的连接部分的宽度基本上等于FPC信号线部分的宽度，并且具有通过将挠曲件和FPC之间的接合中的位置误差乘以2而确定的长度，并将结果加到 FPC布线结构的连接部分。 FPC布线结构的连接部分的宽度基本上等于挠曲布线结构的宽度，并且具有通过将位置误差乘以2而确定的长度，并将结果与​​弯曲布线结构的连接部分的宽度相加。 柔性布线结构的连接部分与FPC布线结构的连接部分成直角相交，并与之连接。

公开(公告)号：US06219255B1

公开(公告)日：2001-04-17

申请号：US09137472

申请日：1998-08-20

Applicant: Abeye Teshome

Inventor： Abeye Teshome

IPC: H05K111

CPC classification number: H05K1/0253 ,  H05K1/0216 ,  H05K1/0262 ,  H05K9/0039 ,  H05K2201/09245 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09663 ,  H05K2201/09781 ,  H05K2201/10689 ,  Y10T29/49155

Abstract: A computer system includes a microprocessor, an an input coupled to provide signal inputs to the microprocessor, a mass storage coupled to the microprocessor, a video controller for coupling the microprocessor to a display, a memory coupled to provide storage to facilitate execution of computer programs by the microprocessor, and a multilayer printed circuit board for mounting the microprocessor thereon. The multilayer printed circuit board provides for reduced electromagnetic interference (EMI) and includes at least two layers. The multilayer printed circuit board further includes a first conductive segment on a first layer, a second conductive segment on the first layer, the second segment being separated from the first segment by a primary gap, and a conductive interconnect on a second layer, the interconnect for carrying a high frequency signal therein. The second layer is disposed laterally from and substantially parallel to the first layer. The interconnect is further disposed for crossing over the first segment to the second segment in a cross-over region and wherein the first segment and the second segment are further characterized by a secondary gap in the cross-over region, the secondary gap being less than the primary gap for providing an increased coupling in the cross-over region. A method for reducing a source of EMI in a multilayer printed circuit board is also disclosed.

Abstract translation: 计算机系统包括微处理器，耦合以向微处理器提供信号输入的输入，耦合到微处理器的大容量存储器，用于将微处理器耦合到显示器的视频控制器，耦合以提供存储以便于执行计算机程序的存储器 以及用于在其上安装微处理器的多层印刷电路板。 多层印刷电路板提供降低的电磁干扰（EMI）并且包括至少两层。 所述多层印刷电路板还包括第一层上的第一导电段，所述第一层上的第二导电区段，所述第二区段通过初级间隙与所述第一区段分离，以及在第二层上的导电互连，所述互连 用于在其中携带高频信号。 第二层从第一层横向设置并基本平行于第一层。 所述互连被进一步布置成用于在交叉区域中跨越所述第一段到所述第二段，并且其中所述第一段和所述第二段的进一步特征在于所述交叉区域中的次级间隙，所述次级间隙小于 用于在交叉区域中提供增加的耦合的主要间隙。 还公开了一种用于减少多层印刷电路板中的EMI源的方法。

公开(公告)号：US5679027A

公开(公告)日：1997-10-21

申请号：US393005

申请日：1995-05-03

Applicant: Robert James Edward Smith

Inventor： Robert James Edward Smith

IPC: H05K1/02 ,  H01R23/02

CPC classification number: H05K1/0228 ,  H01R13/6461 ,  H01R13/6466 ,  H01R13/6467 ,  H01R13/6474 ,  H01R12/51 ,  H01R24/64 ,  H05K2201/09245 ,  Y10S439/941

Abstract: The invention provides a means of reducing crosstalk in data connectors and includes a first conductive signal path and a second conductive signal path. The first signal path includes crossover connection means for changing over the position of the first signal path at a point intermediate between the ends of the first and second paths to reduce crosstalk in the first and second paths through the introduction of antiphase signals. In practice this antiphase crosstalk can be applied by a network of PCB tracks (36) to simulate the conductors.

Abstract translation: PCT No.PCT / GB93 / 01840 Sec。 371日期：1995年5月3日 102（e）日期1995年5月3日PCT提交1993年8月31日PCT公布。 出版物WO94 / 06216 日期：1994年3月17日本发明提供减少数据连接器串扰的方法，包括第一导电信号路径和第二导电信号路径。 第一信号路径包括交叉连接装置，用于在第一和第二路径的端部之间的中间点改变第一信号路径的位置，以通过引入反相信号来减少第一和第二路径中的串扰。 在实践中，这种反相串扰可以通过PCB轨迹（36）的网络来应用以模拟导体。

公开(公告)号：US5470244A

公开(公告)日：1995-11-28

申请号：US132015

申请日：1993-10-05

Applicant: Gunsang Lim ,  Richard D. Marowsky ,  Ben Khoshnood

Inventor： Gunsang Lim ,  Richard D. Marowsky ,  Ben Khoshnood

IPC: H01R13/33 ,  H01R13/6466 ,  H01R13/6467 ,  H01R13/6474 ,  H04M1/03 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H05K1/16 ,  H05K3/40 ,  H01R21/22

CPC classification number: H01R13/6466 ,  H01R13/6467 ,  H01R13/6474 ,  H05K1/0228 ,  H05K1/0393 ,  H05K1/118 ,  H05K1/162 ,  H05K2201/09245 ,  H05K3/403 ,  H05K3/4092 ,  Y10S439/941 ,  Y10T29/4973

Abstract: An electrical connector (30) having crosstalk reduction between selected pairs of electrical contacts comprises a printed circuit board (36, 36') having a pair of circuit elements (40, 42) therein connected through welding pads to selected contacts (6, 3) the connector. The signal paths of such selected contacts are severed and then are re-routed by means of the pattern of circuit elements in the printed circuit board, each circuit element balancing the mutual inductance in such re-routed signal paths for enhanced crosstalk reduction.

Abstract translation: 在所选择的电触头对之间具有串扰减小的电连接器（30）包括具有一对电路元件（40,42）的印刷电路板（36,36'），所述电路元件（40,42）通过焊盘连接到所选择的触点（6,3） 连接器。 这些选择的触点的信号路径被切断，然后通过印刷电路板中的电路元件的图案重新布线，每个电路元件平衡这些重新布线的信号路径中的互感，以增强串扰降低。

公开(公告)号：US5432485A

公开(公告)日：1995-07-11

申请号：US278162

申请日：1994-07-21

Applicant: Katsuya Nagashima

Inventor： Katsuya Nagashima

IPC: H01P1/00 ,  H01P3/08 ,  H01P5/16 ,  H05K1/02 ,  H05K3/46 ,  H01P5/12

CPC classification number: H05K1/0237 ,  H01P5/16 ,  H01L2223/6627 ,  H01L2924/15192 ,  H01L2924/1903 ,  H05K2201/09245 ,  H05K2201/09254

Abstract: A cross circuit comprises a lattice structure formed on a single layer of a multilayer printed circuit, the lattice structure having an arrangement of nodes consisting of two input nodes, two output nodes, a center node and four other nodes which are connected by quarter-wavelength lines. An input node is connected to both a first node and a second node by a quarter-wavelength line, and the other input node is connected to both the first node and a third node by a quarter-wavelength line. Similarly, an output node is connected to both the third node and a fourth node, the other output node to both the fourth node and the second node, the center node to the four nodes, by quarter-wavelength lines, respectively. A first input signal of a predetermined frequency applied to the first input node appears on only the first output node, and the second input signal of the same frequency applied to the second input node appears on only the second output node.

Abstract translation: 交叉电路包括形成在多层印刷电路的单层上的晶格结构，所述晶格结构具有由两个输入节点，两个输出节点，中心节点和四个其他节点组成的节点的布置，所述节点由四分之一波长 线条。 输入节点通过四分之一波长的线连接到第一节点和第二节点，另一个输入节点通过四分之一波长的线连接到第一节点和第三节点。 类似地，输出节点分别连接到第三节点和第四节点，另一个输出节点连接到第四节点和第二节点，中心节点连接到四个节点，四分之一波长线。 施加到第一输入节点的预定频率的第一输入信号仅出现在第一输出节点上，并且施加到第二输入节点的相同频率的第二输入信号仅出现在第二输出节点上。