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    INTEGRATED CONTROL FOR SILICON PHOTONICS
    122.
    发明申请
    INTEGRATED CONTROL FOR SILICON PHOTONICS 有权
    硅光电综合控制

    公开(公告)号：US20170005731A1

    公开(公告)日：2017-01-05

    申请号：US15268239

    申请日：2016-09-16

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. NAGARAJAN

    IPC: H04B10/40 ,  H04B10/54 ,  H03L7/08 ,  H04B10/556

    CPC classification number: H04B10/40 ,  H01S5/0261 ,  H01S5/0427 ,  H03L7/0807 ,  H03L2207/50 ,  H04B10/07955 ,  H04B10/541 ,  H04B10/5561 ,  H04B10/70 ,  H04B10/801 ,  H04J14/0221 ,  H04L49/109

    Abstract: In an example, the present invention includes an integrated system on chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. The device also has an interface configured to communicate between the silicon photonics device and the control block.

    Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 该器件配置在单个硅衬底构件上。 该设备具有设置在基板部件上的数据输入/输出接口。 该装置具有设置在基板部件上并与数据输入/输出接口耦合的输入/输出块。 该装置具有设置在基板构件上并耦合到输入/输出块的信号处理块。 该装置具有设置在基板部件上并与信号处理块相连的驱动器模块。 在一个示例中，该设备具有设置在该衬底构件上的驱动器接口并且耦合到该驱动器模块并被配置为耦合到硅光子器件。 该器件还具有被配置为在硅光子器件和控制块之间通信的接口。

    CIRCUIT AND METHOD FOR PERFORMING ADAPTION ON ALL RECEIVER BRANCHES
    123.
    发明申请
    CIRCUIT AND METHOD FOR PERFORMING ADAPTION ON ALL RECEIVER BRANCHES 有权
    在所有接收器分支上执行自适应的电路和方法

    公开(公告)号：US20160380784A1

    公开(公告)日：2016-12-29

    申请号：US15260692

    申请日：2016-09-09

    Applicant: INPHI CORPORATION

    Inventor： Stephane DALLAIRE ,  Benjamin P. SMITH ,  Travis William LOVITT ,  Arash FARHOODFAR

    IPC: H04L25/03 ,  H04L25/06 ,  H04B1/10 ,  H04L12/26

    CPC classification number: H04L25/03019 ,  H04B1/10 ,  H04L25/03057 ,  H04L25/061 ,  H04L43/028 ,  H04L2025/03363 ,  H04Q2213/03

    Abstract: Receiver circuitry is disclosed that can take circuit branches offline to possibly adapt an offset value. In one embodiment, a circuit in a receiver has at least two branches. Each branch includes an adjustor to adjust the branch signal by an offset value. Selection circuitry takes one of the branches offline by selecting the output of that branch as an offline value, and by selecting the output of one or more of the other branches as a data decision value. The selection circuitry changes which branch is taken offline during the operation of the circuit. When a branch is taken offline, an offset value associated with that branch may be updated, if necessary.

    Abstract translation: 公开了可以使电路分支离线以适应偏移值的接收器电路。 在一个实施例中，接收器中的电路具有至少两个分支。 每个分支包括调整器，以通过偏移值来调整分支信号。 选择电路通过选择该分支的输出作为离线值，并通过选择一个或多个其他分支的输出作为数据判定值，使其中一个分支离线。 选择电路在电路运行期间改变哪个分支脱机。 当分支脱机时，如果需要，可以更新与该分支相关联的偏移值。

    FREQUENCY ACQUISITION FOR SERDES RECEIVERS
    124.
    发明申请
    FREQUENCY ACQUISITION FOR SERDES RECEIVERS 有权
    频率接收服务器接收器

    公开(公告)号：US20160330015A1

    公开(公告)日：2016-11-10

    申请号：US15214212

    申请日：2016-07-19

    Applicant: INPHI CORPORATION

    Inventor： Simon FOREY ,  Parmanand MISHRA ,  Sean BATTY

    IPC: H04L7/00 ,  H04L27/152

    CPC classification number: H04L7/0087 ,  H03M9/00 ,  H04B10/6164 ,  H04L7/0004 ,  H04L7/0331 ,  H04L7/06 ,  H04L27/152

    Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a method for acquiring sampling frequency by sweeping through a predetermined frequency range, performing data sampling at different frequencies within the predetermined frequency range, and determining a target frequency for sampling data based on a maximum early peak frequency and a maximum late peak frequency. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信。 更具体地，本发明的实施例提供一种通过扫过预定频率范围来获取采样频率的方法，在预定频率范围内以不同频率执行数据采样，并且基于最大早峰频率来确定用于采样数据的目标频率 和最大晚峰频率。 还有其它实施例。

    OFF QUADRATURE BIASING OF MACH ZEHNDER MODULATOR FOR IMPROVED OSNR PERFORMANCE
    125.
    发明申请
    OFF QUADRATURE BIASING OF MACH ZEHNDER MODULATOR FOR IMPROVED OSNR PERFORMANCE 有权
    关闭用于改进OSNR性能的MACH ZEHNDER调节器的正交偏置

    公开(公告)号：US20160327816A1

    公开(公告)日：2016-11-10

    申请号：US15072866

    申请日：2016-03-17

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. NAGARAJAN ,  Hari SHANKAR ,  Masaki KATO ,  Yang FU

    IPC: G02F1/01 ,  H01S3/067 ,  H01S3/16 ,  G02F1/225

    CPC classification number: G02F1/0123 ,  G02B6/12007 ,  G02F1/0147 ,  G02F1/025 ,  G02F1/225 ,  G02F1/2255 ,  G02F2001/212 ,  G02F2202/105 ,  H01S3/06754 ,  H01S3/1608 ,  H01S5/0085 ,  H01S5/0687 ,  H01S5/4012 ,  H01S5/4087 ,  H04B10/505 ,  H04B10/50575

    Abstract: An integrated optical modulator device. The device can include a driver module coupled to an optical modulator. The optical modulator is characterized by a raised cosine transfer function. This optical modulator can be coupled to a light source and a bias control module, which is configured to apply an off-quadrature bias to the optical modulator. This bias can be accomplished by applying an inverse of the modulator transfer function to the optical modulator in order to minimize a noise variance. This compression function can result in an optimized increased top eye opening for a signal associated with the optical modulator. Furthermore, the optical modulator can be coupled to an EDFA (Erbium Doped Fiber Amplifier) that is coupled to a filter coupled an O/E (Optical-to-Electrical) receiver.

    Abstract translation: 集成光调制器装置。 该装置可以包括耦合到光调制器的驱动器模块。 光调制器的特征在于升高的余弦传递函数。 该光调制器可以耦合到光源和偏置控制模块，该偏置控制模块被配置为向光调制器施加非正交偏置。 可以通过将调制器传递函数的反相应用于光调制器来实现该偏置，以便最小化噪声方差。 该压缩功能可以导致用于与光学调制器相关联的信号的优化的增加的顶部眼睛开度。 此外，光调制器可以耦合到耦合到耦合到O / E（光 - 电）接收器的滤波器的EDFA（掺铒光纤放大器）。

    Phase interpolator
    126.
    发明授权
    Phase interpolator 有权

    公开(公告)号：US09485086B2

    公开(公告)日：2016-11-01

    申请号：US14872327

    申请日：2015-10-01

    Applicant: INPHI CORPORATION

    Inventor： James L. Gorecki ,  Jiayun Zhang ,  Marcial K. Chua ,  Cosmin Iorga

    IPC: H03H11/16 ,  H04L7/04 ,  H03L7/00 ,  H03K5/01 ,  H03K5/135 ,  H03K5/00

    CPC classification number: H04L7/04 ,  H03K5/01 ,  H03K5/135 ,  H03K2005/00052 ,  H03K2005/00286 ,  H03L7/00 ,  H03L7/0807

    Abstract: Apparatus to implement several high performance phase interpolators are disclosed. Some embodiments are directed to a full-wave integrating phase interpolation core comprising two pairs of in-phase and quadrature-phase current DACs arranged in a cascode architecture to drive an integrating capacitor and produce an interpolation voltage waveform. The current DACs are biased, weighted, and controlled by in-phase and quadrature-phase input clocks to yield an interpolation waveform that presents a phase value between the phases of the input clocks. Some embodiments deploying the interpolator core use feedback circuitry and reference voltages to adjust the common mode and amplitude of the interpolation voltage waveform to obtain both optimal performance and operation within the interpolator linear region or output compliance range. Both the single-core and dual-core implementations, as well as other implementations of the interpolator core, exhibit high power supply rejection, highly linear interpolation, a wide frequency range, and low cost duty cycle correction.

    PAM data communication with reflection cancellation
    127.
    发明授权
    PAM data communication with reflection cancellation 有权
    具有反射消除的PAM数据通信

    公开(公告)号：US09485058B2

    公开(公告)日：2016-11-01

    申请号：US14985243

    申请日：2015-12-30

    Applicant: INPHI CORPORATION

    Inventor： Jamal Riani ,  Sudeep Bhoja

    IPC: H04L25/03 ,  H04L1/00 ,  H04Q11/00 ,  H04L27/06

    CPC classification number: H04L25/03 ,  H04L1/004 ,  H04L1/0061 ,  H04L5/0048 ,  H04L25/03057 ,  H04L25/03885 ,  H04L25/4917 ,  H04L27/04 ,  H04L27/06 ,  H04L2025/03636 ,  H04Q11/0062 ,  H04Q2011/0088

    Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide a communication system that removes reflection signals. A digital data stream is processed through both tentative path and the main path. The tentative path uses a first DFE device and a reflection cancellation circuit to generate a correction signal for removing reflection signal from the digital data stream. A second DFE device removes ISI and other noises from the corrected digital data stream. There are other embodiments as well.

    Abstract translation: 本发明涉及数据通信系统和方法。 更具体地，本发明的实施例提供一种消除反射信号的通信系统。 通过临时路径和主路径处理数字数据流。 暂定路径使用第一DFE装置和反射消除电路来产生用于从数字数据流中去除反射信号的校正信号。 第二个DFE设备从校正的数字数据流中去除ISI和其他噪声。 还有其它实施例。

    Data clock synchronization in hybrid memory modules
    129.
    发明授权
    Data clock synchronization in hybrid memory modules 有权
    混合内存模块中的数据时钟同步

    公开(公告)号：US09460791B1

    公开(公告)日：2016-10-04

    申请号：US14963082

    申请日：2015-12-08

    Applicant: INPHI CORPORATION

    Inventor： Aws Shallal ,  Larry Grant Giddens

    IPC: G11C7/22 ,  G11C7/10 ,  G11C11/4076 ,  G11C14/00 ,  G11C16/32 ,  G11C7/08

    CPC classification number: G11C14/0018 ,  G06F1/08 ,  G06F3/0611 ,  G06F3/0655 ,  G06F3/0688 ,  G11C5/04 ,  G11C7/08 ,  G11C7/10 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/005 ,  G11C11/4076 ,  G11C16/32 ,  G11C29/023 ,  G11C29/028

    Abstract: Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller. In other embodiments, certain fixed and/or programmable delay elements can be implemented to compensate for various asynchronous delays.

    Abstract translation: 这里公开了用于在混合存储器模块中实现数据时钟同步的技术。 实施例包括在命令缓冲器处的时钟同步引擎，以产生具有与来自非易失性存储器控制器的数据信号相位关系的同步数据时钟，该非易失性存储器控制器补偿各种同步和/或异步延迟以促进在某些DRAM处的数据信号的锁存 设备（例如，在数据恢复操作期间）。 其他实施例包括一个分频器，用于通过将来自非易失性存储器控制器的本地时钟信号除以所选择的分频值来确定同步数据时钟的频率。 一些实施例包括一组同步逻辑，其响应于从非易失性存储器控制器接收到特定的本地命令和/或帧脉冲来调用生成同步的数据时钟信号。 在其他实施例中，可以实现某些固定和/或可编程延迟元件来补偿各种异步延迟。

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