公开(公告)号：US20150348945A1

公开(公告)日：2015-12-03

申请号：US14821683

申请日：2015-08-07

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak C. Sekar ,  Zeev Wurman ,  Israel Beinglass

IPC: H01L25/065 ,  H01L23/532 ,  H01L29/45 ,  H01L27/088 ,  H01L27/06 ,  H01L23/544 ,  H01L23/522

CPC classification number: H01L21/6835 ,  G11C8/16 ,  H01L21/743 ,  H01L21/76254 ,  H01L21/76898 ,  H01L21/8221 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7843 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2924/00011 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/80001

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a first interconnection layer interconnecting the first transistors and overlying the first layer; and a second layer including second transistors, where the second layer thickness is less than 2 microns and greater than 5 nm, where the second layer is overlying the first interconnection layer, and where the second layer includes dice lines formed by an etch step.

Abstract translation: 一种3D半导体器件，包括：包括第一晶体管的第一层; 互连第一晶体管并覆盖第一层的第一互连层; 以及包括第二晶体管的第二层，其中所述第二层厚度小于2微米且大于5nm，其中所述第二层覆盖所述第一互连层，并且其中所述第二层包括通过蚀刻步骤形成的管芯线。

公开(公告)号：US20150249053A1

公开(公告)日：2015-09-03

申请号：US14626563

申请日：2015-02-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist

IPC: H01L23/538 ,  H01L27/088 ,  H01L27/06

CPC classification number: H01L23/5386 ,  H01L27/0688 ,  H01L27/085 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/10802 ,  H01L27/1108 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1675 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A semiconductor device including: a first layer including first transistors including at least one first monocrystalline silicon transistor channel; a second layer including second transistors including at least one second monocrystalline non-silicon transistor channel; a plurality of connection paths extending from the second transistors to the first transistors, where at least one of the connection paths includes at least one through layer via with a diameter of less than 200 nm.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一层，所述第一晶体管包括至少一个第一单晶硅晶体管沟道; 第二层，包括包括至少一个第二单晶非硅晶体管沟道的第二晶体管; 从第二晶体管延伸到第一晶体管的多个连接路径，其中至少一个连接路径包括直径小于200nm的至少一个贯穿层通孔。

公开(公告)号：US20150205903A1

公开(公告)日：2015-07-23

申请号：US14672202

申请日：2015-03-29

Applicant: MONOLITHIC 3D INC.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing partitioning to at least a first strata and a second strata; then performing a first placement of the first strata using a 2D placer executed by a computer, where the 2D placer is a Computer Aided Design (CAD) tool currently used in the industry for two-dimensional devices; and performing a second placement of the second strata based on the first placement, where the partitioning includes a partition between logic and memory, and where the logic includes at least one decoder representation for the memory.

Abstract translation: 一种设计3D集成电路的方法，所述方法包括：对至少第一层和第二层进行划分; 然后使用由计算机执行的2D放样器来执行第一层的第一放置，其中2D贴片是当前在工业中用于二维器件的计算机辅助设计（CAD）工具; 以及基于所述第一布置执行所述第二层的第二布置，其中所述分区包括逻辑和存储器之间的分区，以及所述逻辑包括用于所述存储器的至少一个解码器表示。

公开(公告)号：US09030858B2

公开(公告)日：2015-05-12

申请号：US13624968

申请日：2012-09-23

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist ,  Paul Lim

IPC: G11C11/34 ,  H01L27/108 ,  G11C5/02 ,  G11C5/06 ,  H01L27/06 ,  H01L29/78 ,  G11C11/406 ,  H01L23/00 ,  H01L27/02

CPC classification number: H01L27/10873 ,  G11C5/025 ,  G11C5/063 ,  G11C11/406 ,  G11C2211/4016 ,  H01L24/16 ,  H01L24/94 ,  H01L27/0203 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/10894 ,  H01L27/10897 ,  H01L29/7841 ,  H01L29/785 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12033 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2224/81 ,  H01L2924/00

Abstract: A semiconductor device, including: a first semiconductor layer including first transistors, wherein the first transistors are interconnected by at least one metal layer including aluminum or copper; and a second mono-crystallized semiconductor layer including second transistors and overlaying the at least one metal layer, wherein the at least one metal layer is in-between the first semiconductor layer and the second mono-crystallized semiconductor layer, wherein the second mono-crystallized semiconductor layer is less than 100 nm in thickness, and wherein the second transistors include horizontally oriented transistors.

Abstract translation: 一种半导体器件，包括：包括第一晶体管的第一半导体层，其中所述第一晶体管通过包括铝或铜的至少一个金属层互连; 以及包括第二晶体管并覆盖所述至少一个金属层的第二单结晶半导体层，其中所述至少一个金属层位于所述第一半导体层和所述第二单结晶半导体层之间，其中所述第二单结晶半导体层 半导体层的厚度小于100nm，其中第二晶体管包括水平取向的晶体管。

公开(公告)号：US09021414B1

公开(公告)日：2015-04-28

申请号：US13862537

申请日：2013-04-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077

Abstract: A method of designing a 3D Integrated Circuit, the method including: performing placement using a 2D placer, performing placement for at least a first strata and a second strata, and then performing routing and completing the physical design of said 3D Integrated Circuit.

Abstract translation: 一种设计3D集成电路的方法，所述方法包括：使用2D放置器执行放置，执行至少第一层和第二层的放置，然后执行路由并完成所述3D集成电路的物理设计。

公开(公告)号：US08993385B1

公开(公告)日：2015-03-31

申请号：US14491489

申请日：2014-09-19

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Zeev Wurman

IPC: H01L21/84 ,  H01L23/482 ,  H01L21/302 ,  H01L21/268 ,  H01L21/8238 ,  H01L21/8232

CPC classification number: H01L23/4827 ,  H01L21/268 ,  H01L21/302 ,  H01L21/76232 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/481 ,  H01L23/49827 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11807 ,  H01L27/1203 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/01066 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

Abstract: A method to construct a semiconductor device, the method including: forming a first layer including mono-crystallized semiconductor and first logic circuits; forming a second layer including a mono-crystallized semiconductor layer, the second layer overlying the first logic circuits; forming transistors on the second layer; forming connection paths from the second transistors to the first transistors, where the connection paths include a through layer via of less than 200 nm diameter; and connecting the first logic circuits to an external device using input/output (I/O) circuits, the input/output (I/O) circuits are constructed on the second mono-crystallized semiconductor layer.

Abstract translation: 一种构造半导体器件的方法，所述方法包括：形成包括单结晶半导体的第一层和第一逻辑电路; 形成包括单结晶半导体层的第二层，所述第二层覆盖所述第一逻辑电路; 在第二层上形成晶体管; 形成从第二晶体管到第一晶体管的连接路径，其中连接路径包括直径小于200nm的贯穿层通孔; 并且使用输入/输出（I / O）电路将第一逻辑电路连接到外部设备，所述输入/输出（I / O）电路构造在第二单结晶半导体层上。

公开(公告)号：US08703597B1

公开(公告)日：2014-04-22

申请号：US13869963

申请日：2013-04-25

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/44 ,  H01L21/82 ,  H01L21/822

CPC classification number: H01L21/76898 ,  H01L21/268 ,  H01L21/76254 ,  H01L21/84 ,  H01L23/481 ,  H01L24/05 ,  H01L27/0623 ,  H01L27/0688 ,  H01L27/082 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/66545 ,  H01L29/785 ,  H01L2224/0401 ,  H01L2224/16225 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/15788 ,  H01L2924/16152 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for fabricating a device, the method including: providing a first layer including first transistors, where the first transistors include a mono-crystalline semiconductor; overlaying a second semiconductor layer over the first layer; fabricating a plurality of memory cell control lines where the control lines include a portion of the second layer; where the second layer includes second transistors, where the second transistors include a mono-crystalline semiconductor, and where the second transistors are configured to be memory cells.

Abstract translation: 一种制造器件的方法，所述方法包括：提供包括第一晶体管的第一层，其中所述第一晶体管包括单晶半导体; 在第一层上覆盖第二半导体层; 制造多个存储单元控制线，其中控制线包括第二层的一部分; 其中第二层包括第二晶体管，其中第二晶体管包括单晶半导体，并且其中第二晶体管被配置为存储单元。

公开(公告)号：US08574929B1

公开(公告)日：2013-11-05

申请号：US13678584

申请日：2012-11-16

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L21/477

CPC classification number: H01L27/0688 ,  H01L21/76254 ,  H01L27/088 ,  H01L27/092

Abstract: A method to form a monolithic 3D device including: processing a first layer including first mono-crystal transistors; transferring a second mono-crystal layer on top of the first layer including first mono-crystal transistors by using ion-cut layer transfer; and repairing the damage caused by the ion-cut by using optical annealing.

Abstract translation: 一种形成单片3D器件的方法，包括：处理包括第一单晶晶体管的第一层; 通过使用离子切割层转印在包括第一单晶体晶体管的第一层的顶部上转移第二单晶层; 并通过光学退火修复由离子切割引起的损伤。

公开(公告)号：US20130119557A1

公开(公告)日：2013-05-16

申请号：US13683344

申请日：2012-11-21

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L23/48

CPC classification number: H01L21/8221 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/823828 ,  H01L21/84 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5252 ,  H01L24/05 ,  H01L24/13 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11807 ,  H01L27/11898 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/4236 ,  H01L29/66272 ,  H01L29/66621 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/66901 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/7881 ,  H01L29/792 ,  H01L2221/68368 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83894 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01066 ,  H01L2924/01068 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/16152 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00015 ,  H01L2924/01031 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: Two systems including: a first system including a first die connected to a second die; and a second system including a third die connected to a fourth die; wherein the connected includes at least one through silicon via (TSV), and wherein the first die is substantially the same as the third die, and the second die is substantially different than the fourth die.

Abstract translation: 两个系统包括：第一系统，包括连接到第二管芯的第一管芯; 以及第二系统，包括连接到第四管芯的第三管芯; 其中所述连接件包括至少一个贯通硅通孔（TSV），并且其中所述第一管芯基本上与所述第三管芯相同，并且所述第二管芯基本上不同于所述第四管芯。

公开(公告)号：US12249538B2

公开(公告)日：2025-03-11

申请号：US18228907

申请日：2023-08-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/74

Abstract: A 3D device includes a first level including a first single crystal layer with control circuitry, where the control circuitry includes first single crystal transistors; a first metal layer atop first single crystal layer; a second metal layer atop the first metal layer; a third metal layer atop the second metal layer; second level (includes a plurality of second transistors, including metal gate) atop the third metal layer; a fourth metal layer above the one second level; a fifth metal layer atop the fourth metal layer, where the second level includes at least one first oxide layer overlaid by a transistor layer and then overlaid by a second oxide layer; a global power distribution grid including the fifth metal layer; a local power distribution grid, the thickness of the fifth metal layer is at least 50% greater than the thickness of the second metal layer, a layer deposited by ALD.