公开(公告)号：US10083971B1

公开(公告)日：2018-09-25

申请号：US15654190

申请日：2017-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Manfred Eller ,  Kwan-Yong Lim

IPC: H01L27/11 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/785

Abstract: A vertical SRAM cell includes a first (1st) inverter having a 1st common gate structure operatively connecting channels of a 1st pull-up (PU) and a 1st pull-down (PD) transistor. A 1st metal contact electrically connects bottom source/drain (S/D) regions of the 1st PU and 1st PD transistors. A second (2nd) inverter has a 2nd common gate structure operatively connecting channels of a 2nd PU and a 2nd PD transistor. A 2nd metal contact electrically connects bottom S/D regions of the 2nd PU and 2nd PD transistors. A 1st cross-coupled contact electrically connects the 2nd common gate structure to the 1st metal contact. The 2nd common gate structure entirely surrounds a perimeter of the 1st cross-coupled contact. A 2nd cross-coupled contact electrically connects the 1st common gate structure to the 2nd metal contact. The 1st common gate structure entirely surrounds a perimeter of the 2nd cross-coupled contact.

公开(公告)号：US20180240884A1

公开(公告)日：2018-08-23

申请号：US15961264

申请日：2018-04-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L29/78 ,  H01L27/12 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US10038096B2

公开(公告)日：2018-07-31

申请号：US14847462

申请日：2015-09-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi

IPC: H01L21/336 ,  H01L21/76 ,  H01L21/311 ,  H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7853 ,  H01L21/76224 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/66818

Abstract: A three-dimensional transistor includes a channel with a center portion (forked channel) or side portions (narrow channel) removed, or fins without shaping, after removal of the dummy gate and before a replacement metal gate is formed.

公开(公告)号：US10026740B1

公开(公告)日：2018-07-17

申请号：US15797533

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Jerome Ciavatti ,  Josef Watts

IPC: H01L27/108 ,  H01L29/06

Abstract: One illustrative DRAM structure disclosed herein includes a first memory cell pair, a second memory cell pair, a single diffusion break (SDB) isolation structure positioned between the first and second memory cell pairs, and a single first gate positioned between the first and second memory cell pairs and above the SDB isolation structure.

公开(公告)号：US10014298B1

公开(公告)日：2018-07-03

申请号：US15844840

申请日：2017-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haigou Huang ,  Xiaofeng Qiu

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/49 ,  H01L21/762 ,  H01L21/28

CPC classification number: H01L27/0886 ,  H01L21/28123 ,  H01L21/31053 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823871 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/78651

Abstract: In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates (RMGs) and replacement metal contacts (RMCs), gate cut trench(es) and contact cut trench(es) are formed at the same process level. These trench(es) are then filled at the same time with the same isolation material to form gate cut isolation region(s) for electrically isolating adjacent RMGs and contact cut isolation region(s) for electrically isolating adjacent RMCs, respectively. The selected isolation material can be a low-K isolation material for optimal performance. Furthermore, since the same process step is used to fill both types of trenches, only a single chemical mechanical polishing (CMP) process is needed to remove the isolation material from above the gate level, thereby minimizing gate height loss and process variation. Also disclosed herein is an IC structure formed according to the method.

公开(公告)号：US10002940B2

公开(公告)日：2018-06-19

申请号：US15363563

申请日：2016-11-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Hyun-Jin Cho ,  Tenko Yamashita ,  Hui Zang

IPC: H01L29/51 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L29/512 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/28088 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823864 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a gate structure for a semiconductor device that includes forming first spacers on the sidewalls of replacement gate structures that are present on a fin structure, wherein an upper surface of the first spacers is offset from an upper surface of the replacement gate structure, and forming at least second spacers on the first spacers and the exposed surfaces of the replacement gate structure. The method may further include substituting the replacement gate structure with a functional gate structure having a first width portion in a first space between adjacent first spacers, and a second width portion having a second width in a second space between adjacent second spacers, wherein the second width is greater than the first width.

公开(公告)号：US20180151449A1

公开(公告)日：2018-05-31

申请号：US15361809

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Rinus T. P. Lee ,  Bharat V. Krishnan ,  Hui Zang ,  Matthew W. Stoker

IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/32 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/02362 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/32 ,  H01L29/785

Abstract: One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.

公开(公告)号：US20180122891A1

公开(公告)日：2018-05-03

申请号：US15848324

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/3205

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US09923046B1

公开(公告)日：2018-03-20

申请号：US15271730

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US09812368B2

公开(公告)日：2017-11-07

申请号：US15289158

申请日：2016-10-08

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc.

Inventor： Balasubramanian Pranatharthiharan ,  Hui Zang

IPC: H01L21/8236 ,  H01L21/8238 ,  H01L27/11 ,  H01L29/78 ,  H01L21/304 ,  H01L29/66

CPC classification number: H01L27/1104 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/3043 ,  H01L21/324 ,  H01L21/76 ,  H01L21/76224 ,  H01L21/8221 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/1116 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785

Abstract: The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure. Each of the set of fins has respective cut faces located at the fin ends of a set of fin ends. A photoresist layer is patterned over the set of fin ends on the set of fins of the FinFET structure. The set of fins are isolated from one another by a first dielectric material. The photoresist is patterned over the set of fin ends so that it differs from the photoresist pattern over other areas of the FinFET structure. A set of dielectric blocks is formed on the set of fin ends using the photoresist pattern. The set of dielectric blocks prevents epitaxial growth at the set of fin ends in a subsequent epitaxial growth step.