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121.发明授权公开(公告)号：US07560310B2
公开(公告)日：2009-07-14
申请号：US11965445
申请日：2007-12-27
IPC分类号： H01L21/00
CPC分类号： H01L23/3677 , H01L2924/0002 , H01L2924/10158 , Y10S438/928 , Y10S438/96 , Y10S438/977 , H01L2924/00
摘要： A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.
摘要翻译： 一种制造半导体器件的方法包括蚀刻形成在半导体晶片的背面上的衬底，以在衬底中形成凹陷，并且在凹部中形成溅射膜，溅射膜包括具有热膨胀系数的第一材料（ CTE），其至少基本上等于衬底的CTE，以及具有大于衬底的热导率的导热性的第二材料。
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122.发明申请公开(公告)号：US20080224261A1
公开(公告)日：2008-09-18
申请号：US12127080
申请日：2008-05-27
IPC分类号： H01L23/525 , H01L21/44
CPC分类号： H01L23/5256 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided.
摘要翻译： 提供了用于熔丝/反熔丝结构的技术，包括内部导体结构，从内部导体结构向外间隔开的绝缘层，设置在绝缘层外部的外部导体结构，以及限定空腔的空腔限定结构， 其中空腔限定结构的至少一部分由内部导体结构，绝缘层和外部导体狭窄中的至少一个形成。还提供了制造和编程熔丝/反熔丝结构的方法。
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123.发明申请Latch-Up Resistant Semiconductor Structures on Hybrid Substrates and Methods for Forming Such Semiconductor Structures 失效混合基板上的锁定阻抗半导体结构和形成这种半导体结构的方法公开(公告)号：US20080217690A1
公开(公告)日：2008-09-11
申请号：US11680083
申请日：2007-02-28
IPC分类号： H01L21/8238
CPC分类号： H01L29/045 , H01L21/26513 , H01L21/823878 , H01L27/0921 , H01L27/1203 , H01L27/1207 , H01L29/0646 , H01L29/1087
摘要： Latch-up resistant semiconductor structures formed on a hybrid substrate and methods of forming such latch-up resistant semiconductor structures. The hybrid substrate is characterized by first and second semiconductor regions that are formed on a bulk semiconductor region. The second semiconductor region is separated from the bulk semiconductor region by an insulating layer. The first semiconductor region is separated from the bulk semiconductor region by a conductive region of an opposite conductivity type from the bulk semiconductor region. The buried conductive region thereby the susceptibility of devices built using the first semiconductor region to latch-up.
摘要翻译： 在混合基板上形成的耐锁定半导体结构以及形成这种防闩锁半导体结构的方法。 混合衬底的特征在于形成在体半导体区域上的第一和第二半导体区域。 第二半导体区域通过绝缘层与体半导体区域分离。 第一半导体区域通过与体半导体区域相反的导电类型的导电区域与体半导体区域分离。 掩埋的导电区域因此使用第一半导体区域构建的器件的敏感性被闩锁。
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公开(公告)号：US07113006B2
公开(公告)日：2006-09-26
申请号：US11065840
申请日：2005-02-25
CPC分类号： H02M3/07
摘要： A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater than the second voltage. The capacitor further includes a voltage comparator having a first input for receiving a voltage representative of the first voltage, a second input for receiving a third voltage provided by a third source, and an output for generating a control signal. The control signal is a function of a difference between the voltage representative of the first voltage and the third voltage. A switch is connected to second terminals of the first and second capacitors. The switch is selectively operable in one of at least a first mode and a second mode in response to the control signal, wherein in the first mode the switch is operative to connect the first and second capacitors together in parallel, and in the second mode the switch is operative to connect the first and second capacitors together in series. The first mode is indicative of the voltage representative of the first voltage being less than or about equal to the third voltage, and the second mode is indicative of the voltage representative of the first voltage being greater than the third voltage.
摘要翻译： 具有改进的可靠性的电容器电路包括至少第一和第二电容器，第一电容器的第一端子连接到提供第一电压的第一源极，第二电容器的第一端子连接到提供第二电压的第二源极，第一电容器 电压大于第二电压。 电容器还包括电压比较器，具有用于接收表示第一电压的电压的第一输入端，用于接收由第三源极提供的第三电压的第二输入端和用于产生控制信号的输出端。 控制信号是代表第一电压和第三电压的电压之差的函数。 开关连接到第一和第二电容器的第二端子。 响应于控制信号，开关选择性地可操作于至少第一模式和第二模式之一中，其中在第一模式中，开关可操作以并联连接第一和第二电容器，并且在第二模式中， 开关可操作以串联连接第一和第二电容器。 第一模式表示代表第一电压的电压小于或等于第三电压，第二模式表示代表第一电压的电压大于第三电压。
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125.发明授权Structure and method of vertical transistor DRAM cell having a low leakage buried strap 失效具有低泄漏掩埋带的垂直晶体管DRAM单元的结构和方法公开(公告)号：US06979851B2
公开(公告)日：2005-12-27
申请号：US10265558
申请日：2002-10-04
IPC分类号： G11C11/24 , H01L21/8242 , H01L29/76
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.
摘要翻译： 本文公开了一种用于垂直晶体管DRAM单元的结构和方法，该垂直晶体管DRAM单元具有将沟槽下部的存储电容器导电连接到其上方的垂直晶体管的低泄漏掩埋带外扩散。 在所公开的结构和方法中，掩埋带外扩散（BSOD）沿着具有减小的厚度的隔离环的一部分延伸，否则减小的厚度小于隔离环的厚度。 在特定实施例中，形成自对准的轻掺杂漏极（LDD）延伸，在LDD之上的BSOD和垂直晶体管之间延伸。
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126.发明授权Self-aligned, planarized thin-film transistors, devices employing the same, and methods of fabrication thereof 失效自对准的平面化薄膜晶体管，采用该晶体管的器件及其制造方法公开(公告)号：US06818487B2
公开(公告)日：2004-11-16
申请号：US10631533
申请日：2003-07-31
IPC分类号： H01L2100
CPC分类号： H01L29/66787 , H01L27/11 , H01L27/1108 , H01L29/42384 , H01L29/66765 , H01L29/78636
摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized semiconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
摘要翻译： 提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。 半导体器件具有第一场效应晶体管和第二场效应晶体管。 第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。 第二场效应晶体管包括在第一场效应晶体管上方的平坦化半导体材料层中与共享栅极自对准的源极和漏极。 在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。
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127.发明授权公开(公告)号：US06649935B2
公开(公告)日：2003-11-18
申请号：US09795535
申请日：2001-02-28
IPC分类号： H01L2976
CPC分类号： H01L29/66787 , H01L27/11 , H01L27/1108 , H01L29/42384 , H01L29/66765 , H01L29/78636
摘要： A semiconductor device is presented which includes a self-aligned, planarized thin-film transistor which can be used in various integrated circuit devices, such as static random access memory (SRAM) cells. The semiconductor device has a first field-effect transistor and a second field-effect transistor. The second field-effect transistor overlies the first field-effect transistor, and the first field-effect transistor and the second field-effect transistor share a common gate. The second field-effect transistor includes a source and a drain which are self-aligned to the shared gate in a layer of planarized seminconductor material above the first field-effect transistor. In one embodiment, the second field-effect transistor is a thin-film transistor, and the shared gate has a U-shape wrap-around configuration at a body of the thin-film transistor.
摘要翻译： 提出了一种半导体器件，其包括可用于诸如静态随机存取存储器（SRAM）单元的各种集成电路器件中的自对准的平坦化薄膜晶体管。 半导体器件具有第一场效应晶体管和第二场效应晶体管。 第二场效应晶体管覆盖第一场效应晶体管，第一场效应晶体管和第二场效应晶体管共用公共栅极。 第二场效应晶体管包括在第一场效应晶体管之上的平坦化半导体材料层中与共享栅极自对准的源极和漏极。 在一个实施例中，第二场效应晶体管是薄膜晶体管，并且共享栅极在薄膜晶体管的主体处具有U形环绕配置。
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公开(公告)号：US06531410B2
公开(公告)日：2003-03-11
申请号：US09795610
申请日：2001-02-27
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L2131
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.
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129.发明授权Method of controllably forming a LOCOS oxide layer over a portion of a vertically extending sidewall of a trench extending into a semiconductor substrate 失效在延伸到半导体衬底的沟槽的垂直延伸的侧壁的一部分上可控地形成LOCOS氧化物层的方法
公开(公告)号：US6153474A
公开(公告)日：2000-11-28
申请号：US108619
申请日：1998-07-01
申请人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
发明人： Herbert Lei Ho , Radhika Srinivasan , Scott D. Halle , Erwin Hammerl , David M. Dobuzinsky , Jack Allan Mandelman , Mark Anthony Jaso
IPC分类号： H01L27/04 , H01L21/02 , H01L21/762 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/336
CPC分类号： H01L27/10861 , H01L21/76232 , H01L27/10832 , H01L28/82 , Y10S438/973
摘要： The present invention includes a method and system to increase the deep trench sidewall surface area in a storage node on a DRAM chip. By tilting the trenches the capacitance is increased without taking up more space on the semiconductor chip.
摘要翻译： 本发明包括一种用于增加DRAM芯片上的存储节点中的深沟槽侧壁表面积的方法和系统。 通过倾斜沟槽，电容增加，而不占用半导体芯片上的更多空间。
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公开(公告)号：US5831301A
公开(公告)日：1998-11-03
申请号：US14523
申请日：1998-01-28
申请人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
发明人： David Vaclav Horak , Toshiharu Furukawa , Steven John Holmes , Mark Charles Hakey , William Hsioh-Lien Ma , Jack Allan Mandelman
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A memory cell including a substrate, at least one deep trench capacitor in the substrate, at least one FET in the substrate disposed over at least a portion of the at least one deep trench capacitor, and at least one isolation region in the substrate surrounding the at least one FET and having a greater depth than the at least one FET. The at least one FET includes a gate disposed over at least a portion of the at least one deep trench capacitor and doped regions arranged on adjacent sides of the gate and separated from the gate by an insulating layer.
摘要翻译： 存储单元，包括衬底，衬底中的至少一个深沟槽电容器，设置在所述至少一个深沟槽电容器的至少一部分上的所述衬底中的至少一个FET以及所述衬底中的至少一个隔离区域， 至少一个FET并且具有比所述至少一个FET更大的深度。 所述至少一个FET包括设置在所述至少一个深沟槽电容器的至少一部分上的栅极和布置在栅极的相邻侧上的掺杂区域，并且通过绝缘层与栅极分离。
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