公开(公告)号：US11933555B2

公开(公告)日：2024-03-19

申请号：US17509514

申请日：2021-10-25

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H05K7/20 ,  F28F3/02 ,  F28F13/00 ,  H01L23/367 ,  H01L23/373

CPC classification number: F28F3/022 ,  F28F13/003 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/3735 ,  H05K7/2039

Abstract: A heat dissipation device may be formed having at least one isotropic thermally conductive section (uniformly high thermal conductivity in all directions) and at least one anisotropic thermally conductive section (high thermal conductivity in at least one direction and low thermal conductivity in at least one other direction). The heat dissipation device may be thermally coupled to a plurality of integrated circuit devices such that at least a portion of the isotropic thermally conductive section(s) and/or the anisotropic thermally conductive section(s) is positioned over at least one integrated circuit device. The isotropic thermally conductive section(s) allows heat spreading/removal from hotspots or areas with high-power density and the anisotropic thermally conductive section(s) transfers heat away from the at least one integrated circuit device predominately in a single direction with minimum conduction resistance in areas with uniform power density distribution, while reducing heat transfer in the other directions, thereby reducing thermal cross-talk.

公开(公告)号：US20240063180A1

公开(公告)日：2024-02-22

申请号：US17891654

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Kimin Jun ,  Adel Elsherbini ,  Omkar Karhade ,  Bhaskar Jyoti Krishnatreya ,  Mohammad Enamul Kabir ,  Jiraporn Seangatith ,  Tushar Talukdar ,  Shawna Liff ,  Johanna Swan ,  Feras Eid

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/48 ,  H01L23/13 ,  H01L23/31

CPC classification number: H01L25/0652 ,  H01L25/50 ,  H01L21/4857 ,  H01L23/13 ,  H01L23/3185 ,  H01L24/05

Abstract: Quasi-monolithic multi-die composites including a primary fill structure within a space between adjacent IC dies. A fill material layer, which may have inorganic composition, may be bonded to a host substrate and patterned to form a primary fill structure that occupies a first portion of the host substrate. IC dies may be bonded to regions of the host substrate within openings where the primary fill structure is absent to have a spatial arrangement complementary to the primary fill structure. The primary fill structure may have a thickness substantially matching that of IC dies and/or be co-planar with a surface of one or more of the IC dies. A gap fill material may then be deposited within remnants of the openings to form a secondary fill structure that occupies space between the IC dies and the primary fill structure.

公开(公告)号：US20240063071A1

公开(公告)日：2024-02-22

申请号：US17891880

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Jeffery Bielefeld ,  Adel Elsherbini ,  Bhaskar Jyoti Krishnatreya ,  Feras Eid ,  Gauri Auluck ,  Kimin Jun ,  Mohammad Enamul Kabir ,  Nagatoshi Tsunoda ,  Renata Camillo-Castillo ,  Tristan A. Tronic ,  Xavier Brun

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3128 ,  H01L25/0655 ,  H01L24/08 ,  H01L23/367 ,  H01L23/49827 ,  H01L23/49838 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Multi-die composite structures including a multi-layered inorganic dielectric gap fill material within a space between adjacent IC dies. A first layer of fill material with an inorganic composition may be deposited over IC dies with a high-rate deposition process, for example to at least partially fill a space between the IC dies. The first layer of fill material may then be partially removed to modify a sidewall slope of the first layer or otherwise reduce an aspect ratio of the space between the IC dies. Another layer of fill material may be deposited over the lower layer of fill material, for example with the same high-rate deposition process. This dep-etch-dep cycle may be repeated any number of times to backfill spaces between IC dies. The multi-layer fill material may then be globally planarized and the IC die package completed and/or assembled into a next-level of integration.

公开(公告)号：US11887944B2

公开(公告)日：2024-01-30

申请号：US16909258

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Feras Eid ,  Adel Elsherbini

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/544 ,  H01L21/48 ,  H01P11/00 ,  H01P3/06

CPC classification number: H01L23/66 ,  H01L21/4853 ,  H01L21/4871 ,  H01L23/3675 ,  H01L23/49838 ,  H01L23/544 ,  H01L24/16 ,  H01P3/06 ,  H01P11/005 ,  H01L2223/54426 ,  H01L2223/6627 ,  H01L2224/16227

Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.

公开(公告)号：US11842826B2

公开(公告)日：2023-12-12

申请号：US16909264

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Adel Elsherbini ,  Feras Eid ,  Johanna Swan ,  Georgios Dogiamis

IPC: H01L21/786 ,  H01B13/22 ,  H01B13/00 ,  H01B7/00 ,  H01B7/18 ,  H01L21/768 ,  B33Y10/00 ,  B33Y80/00

CPC classification number: H01B13/0036 ,  H01B7/0018 ,  H01B7/1805 ,  H01B13/002 ,  H01B13/0026 ,  H01B13/22 ,  H01L21/76885 ,  B33Y10/00 ,  B33Y80/00

Abstract: Cables, cable connectors, and support structures for cantilever package and/or cable attachment may be fabricated using additive processes, such as a coldspray technique, for integrated circuit assemblies. In one embodiment, cable connectors may be additively fabricated directly on an electronic substrate. In another embodiment, seam lines of cables and/or between cables and cable connectors may be additively fused. In a further embodiment, integrated circuit assembly attachment and/or cable attachment support structures may be additively formed on an integrated circuit assembly.

公开(公告)号：US20230245972A1

公开(公告)日：2023-08-03

申请号：US18132865

申请日：2023-04-10

Applicant: INTEL CORPORATION

Inventor： Adel Elsherbini ,  Shawna Liff ,  Johanna Swan ,  Gerald Pasdast

IPC: H01L23/538 ,  H01L21/304 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/5385 ,  H01L21/3043 ,  H01L21/4846 ,  H01L24/20

Abstract: Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

公开(公告)号：US11688665B2

公开(公告)日：2023-06-27

申请号：US16007269

申请日：2018-06-13

Applicant: Intel Corporation

Inventor： Feras Eid ,  Adel Elsherbini ,  Johanna Swan

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/488 ,  H01L23/46 ,  H01L23/473 ,  H01L25/065 ,  H01L23/498 ,  H01L23/467 ,  H01L23/538

CPC classification number: H01L23/473 ,  H01L23/3157 ,  H01L23/3677 ,  H01L23/467 ,  H01L23/49822 ,  H01L23/5386 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06589

Abstract: An integrated circuit assembly may be formed having a substrate, a first integrated circuit device electrically attached to the substrate, a second integrated circuit device electrically attached to the first integrated circuit device, and a heat dissipation device defining a fluid chamber, wherein at least a portion of the first integrated circuit device and at least a portion of the second integrated circuit device are exposed to the fluid chamber. In further embodiments, at least one channel may be formed in an underfill material between the first integrated circuit device and the second integrated circuit device, between the first integrated circuit device and the substrate, and/or between the second integrated circuit device and the substrate, wherein the at least one channel is open to the fluid chamber.

公开(公告)号：US20230136469A1

公开(公告)日：2023-05-04

申请号：US18092140

申请日：2022-12-30

Applicant: INTEL CORPORATION

Inventor： Johanna Swan ,  Feras Eid ,  Adel Elsherbini

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/42 ,  H01L23/00 ,  H01L21/48

Abstract: An integrated circuit structure may be formed having a substrate, at least one integrated circuit device embedded in and electrically attached to the substrate, and a heat dissipation device in thermal contact with the integrated circuit device, wherein a first portion of the heat dissipation device extends into the substrate and wherein a second portion of the heat dissipation device extends over the substrate. In one embodiment, the heat dissipation device may comprise the first portion of the heat dissipation device formed from metallization within the substrate.

公开(公告)号：US20230098710A1

公开(公告)日：2023-03-30

申请号：US17484329

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Aleksandar Aleksov ,  Feras Eid ,  Adel Elsherbini ,  Wenhao Li ,  Stephen Morein

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/498

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.

公开(公告)号：US20230098303A1

公开(公告)日：2023-03-30

申请号：US17484339

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Yoshihiro Tomita ,  Aleksandar Aleksov ,  Feras Eid ,  Adel Elsherbini ,  Wenhao Li ,  Stephen Morein

IPC: H01L23/532 ,  H01L23/528 ,  H01L23/498 ,  H01L21/768

Abstract: Technologies for high throughput additive manufacturing (HTAM) structures are disclosed. In one embodiment, a sacrificial dielectric is formed to provide a negative mask on which to pattern a conductive trace using HTAM. In another embodiment, a permanent dielectric is patterned using a processing such as laser project patterning. A conductive trace can then be patterned using HTAM. In yet another embodiment, conductive traces with tapered sidewalls can be patterned, and then a buffer layer and HTAM layer can be deposited on top.