公开(公告)号：US20150048480A1

公开(公告)日：2015-02-19

申请号：US13968627

申请日：2013-08-16

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Young Kyu Song ,  Changhan Hobie Yun ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim ,  Xiaonan Zhang ,  Ryan David Lane

IPC: H01L23/498 ,  H01L21/768 ,  H01L49/02

CPC classification number: H01L23/49827 ,  H01L21/76885 ,  H01L23/49816 ,  H01L23/50 ,  H01L23/5222 ,  H01L23/642 ,  H01L28/10 ,  H01L28/20 ,  H01L28/40 ,  H01L2224/16225 ,  H01L2225/06572 ,  H01L2924/19105

Abstract: Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.

Abstract translation: 一些新颖的特征涉及一种半导体器件，其包括衬底，穿过衬底的第一腔体。 第一腔被配置为被互连材料（例如，焊球）占据。 衬底还包括耦合到第一腔的第一侧壁的第一金属层。 衬底还包括在衬底的第一表面上的第一集成无源器件（IPD），第一IPD耦合到第一金属层。 在一些实施方案中，基底是玻璃基底。 在一些实现中，第一IPD是至少一个电容器，电感器和/或电阻器中的一个。 在一些实施方式中，半导体器件还包括在衬底的第二表面上的第二集成无源器件（IPD）。 第二IPD耦合到第一金属层。

公开(公告)号：US20140327510A1

公开(公告)日：2014-11-06

申请号：US13887788

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Daeik D. Kim ,  David F. Berdy ,  Chengjie Zuo ,  Mario Francisco Velez ,  Changhan Yun ,  Robert P. Mikulka ,  Jonghae Kim ,  Je-Hsiung Lan

IPC: H05K9/00 ,  H05K3/10 ,  H05K3/00 ,  H01F5/00 ,  H05K1/11

CPC classification number: H05K9/002 ,  H01F17/0006 ,  H01F27/362 ,  H01F2017/002 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/107

Abstract: An electronic device includes a structure. The structure includes a first set of through glass vias (TGVs) and a second set of TGVs. The first set of TGVs includes a first via and the second set of TGVs includes a second via. The first via has a different cross-sectional shape than the second via.

Abstract translation: 一种电子设备包括一种结构。 该结构包括第一组直通玻璃通孔（TGV）和第二组TGV。 第一组TGV包括第一通孔，第二组TGV包括第二通孔。 第一通孔具有与第二通孔不同的横截面形状。

公开(公告)号：US20140268616A1

公开(公告)日：2014-09-18

申请号：US13833632

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Changhan Yun ,  David F. Berdy ,  Daeik D. Kim ,  Robert P. Mikulka ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/40 ,  G06F17/5068 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L27/016 ,  H01L27/12 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

Abstract translation: 在特定实施例中，器件包括衬底，至少部分延伸穿过衬底的通孔和电容器。 电容器的电介质位于电容器的通孔和板之间，并且电容器的板在衬底外部和器件内部。

公开(公告)号：US20140240072A1

公开(公告)日：2014-08-28

申请号：US13778191

申请日：2013-02-27

Applicant: Qualcomm Incorporated

Inventor： Je-Hsiung Lan ,  Chi Shun Lo ,  Jonghae Kim ,  John H. Hong

IPC: H01F19/00 ,  H01F41/04 ,  H01F5/00

CPC classification number: H01F19/00 ,  H01F5/003 ,  H01F27/2804 ,  H01F41/041 ,  H01F2027/2809 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H05K1/144 ,  H05K3/3436 ,  H05K2201/041 ,  H05K2201/0723 ,  Y10T29/4902 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a low-loss substrate, a first inductor structure, and an air-gap. The first inductor structure is between the low-loss substrate and a second inductor structure. The first inductor structure is aligned with the second inductor structure to form a transformer. The air-gap is between the first inductor structure and the second inductor structure.

Abstract translation: 在特定实施例中，器件包括低损耗衬底，第一电感器结构和气隙。 第一电感器结构在低损耗衬底和第二电感器结构之间。 第一电感器结构与第二电感器结构对准以形成变压器。 气隙位于第一电感结构和第二电感结构之间。

公开(公告)号：US20140167273A1

公开(公告)日：2014-06-19

申请号：US13719984

申请日：2012-12-19

Applicant: QUALCOMM INCORPORATED

Inventor： Jonghae Kim ,  Chengjie Zuo ,  Changhan Yun ,  Mario Francisco Velez ,  Ravindra V. Shenoy ,  Matthew M. Nowak ,  Francesco Carobolante ,  Kyu-Pyung Hwang ,  Dong Wook Kim ,  Young K. Song

IPC: H01L23/482 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01L23/3121 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2221/68345 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/1517 ,  H01L2924/181 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/10015 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

Abstract: One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer.

Abstract translation: 一个特征涉及集成电路封装的多层封装衬底，其包括具有至少一个电极的分立电路部件（DCC）。 DCC嵌入在绝缘体层内，并且通孔耦合部件电耦合到电极。 通孔耦合部件的第一部分延伸超过电极的第一边缘，并且多个通孔各自具有耦合到第一通路耦合部件的第一端。 多个通孔中的至少第一通孔耦合到延伸超出电极的第一边缘的通孔连接部件的第一部分。 此外，多个通孔各自具有电耦合到第一外部金属层的第二端，并且通孔连接部件的至少第二部分位于第一内部金属层内。

公开(公告)号：US20140138792A1

公开(公告)日：2014-05-22

申请号：US13684103

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Chi Shun Lo ,  Je-Hsiung Lan ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H01L49/02 ,  H01L21/00

CPC classification number: H01L28/10 ,  H01F19/04 ,  H01F21/00 ,  H01F2019/085 ,  H01F2027/2809 ,  H01L21/00 ,  H01L23/5227 ,  H01L23/645 ,  H01L2924/0002 ,  Y10T29/41 ,  H01L2924/00

Abstract: Several novel features pertain to a hybrid transformer formed within a semiconductor die having multiple layers. The hybrid transformer includes a first set of windings positioned on a first layer of the die. The first layer is positioned above a substrate of the die. The first set of windings includes a first port and a second port. The first set of windings is arranged to operate as a first inductor. The hybrid transformer includes a second set of windings positioned on a second layer of the die. The second layer is positioned above the substrate. The second set of windings includes a third port, a fourth port and a fifth port. The second set of windings is arranged to operate as a second inductor and a third inductor. The first set of windings and the second set of windings are arranged to operate as a vertical coupling hybrid transformer.

Abstract translation: 几种新颖的特征涉及形成在具有多层的半导体管芯内的混合变压器。 混合变压器包括位于模具的第一层上的第一组绕组。 第一层位于模具的基底之上。 第一组绕组包括第一端口和第二端口。 第一组绕组被布置成作为第一电感器工作。 混合变压器包括位于模具的第二层上的第二组绕组。 第二层位于衬底上方。 第二组绕组包括第三端口，第四端口和第五端口。 第二组绕组被布置成用作第二电感器和第三电感器。 第一组绕组和第二组绕组被布置成作为垂直耦合混合变压器工作。

公开(公告)号：US12283607B2

公开(公告)日：2025-04-22

申请号：US17349724

申请日：2021-06-16

Applicant: QUALCOMM Incorporated

Inventor： Jonghae Kim ,  Je-Hsiung Lan ,  Ranadeep Dutta

IPC: H01F27/28 ,  H01F17/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/66 ,  H01L49/02 ,  H01P3/08 ,  H01P11/00

Abstract: A three dimensional (3D) inductor is described. The 3D inductor includes a first plurality of micro-through substrate vias (TSVs) within a first area of a substrate. The 3D inductor also includes a first trace on a first surface of the substrate, coupled to a first end of the first plurality of micro-TSVs. The 3D inductor further includes a second trace on a second surface of the substrate, opposite the first surface, coupled to a second end, opposite the first end, of the first plurality of micro-TSVs.

公开(公告)号：US20250047262A1

公开(公告)日：2025-02-06

申请号：US18363233

申请日：2023-08-01

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

IPC: H03H9/25 ,  H03H3/08 ,  H03H9/145 ,  H03H9/64

Abstract: An acoustic device includes circuit elements, such as analog circuit components, between the first and second substrate and coupled to an acoustic resonator to form an acoustic filter within the acoustic device. In some examples, forming the circuit elements between the first substrate and the second substrate includes forming the first circuit elements in insulating material on the second substrate before coupling the second substrate to a first side of the first substrate. The circuit elements disposed between the first and second substrates may include capacitors, inductors, and electrical interconnects coupled to the acoustic resonator on the first substrate. Additional features may be included in the insulating material. The acoustic device avoids the need for bulky analog components coupled to the acoustic resonator via long interconnects through a package substrate, making it possible to reduce an acoustic device's package size.

公开(公告)号：US12218041B2

公开(公告)日：2025-02-04

申请号：US17237828

申请日：2021-04-22

Applicant: QUALCOMM Incorporated

Inventor： Jihong Choi ,  Giridhar Nallapati ,  William Stone ,  Jianwen Xu ,  Jonghae Kim ,  Periannan Chidambaram ,  Ahmer Syed

IPC: H01L23/498 ,  H01L21/48 ,  H01L49/02

Abstract: Integrated circuit (IC) packages employing a capacitor-embedded, redistribution layer (RDL) substrate and related fabrication methods. The embedded capacitor can be coupled to a power distribution network (PDN) to provide decoupling capacitance to reduce current-resistance (IR) drop. The RDL substrate is disposed between the IC chip(s) and the package substrate to minimize distance between the embedded capacitor(s) and the IC chip(s) to reduce the parasitic inductance in the PDN, thus reducing PDN noise. With the RDL substrate disposed between the package substrate and the IC chip(s), the RDL substrate needs to support through-interconnections between the package substrate and the IC chip(s). In this regard, the RDL substrate includes an outer RDL layer adjacent to the IC chip(s) to support small pitch metal interconnects as well as provide fan-out capability. This provides enhanced connectivity compatibility with higher-density die interconnect IC chips while also supporting a closer located embedded capacitor in the PDN.

公开(公告)号：US12142561B2

公开(公告)日：2024-11-12

申请号：US17705041

申请日：2022-03-25

Applicant: QUALCOMM Incorporated

Inventor： Kai Liu ,  Je-Hsiung Lan ,  Jonghae Kim

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/00

Abstract: An integrated device that includes a die substrate comprising a plurality of transistors, an interconnection portion coupled to the die substrate, and a packaging portion coupled to the interconnection portion. The interconnection portion includes at least one die dielectric layer and a plurality of die interconnects coupled to the plurality of transistors. The packaging portion includes at least one magnetic layer and a plurality of metallization interconnects coupled to the plurality of die interconnects.