公开(公告)号：US20200343277A1

公开(公告)日：2020-10-29

申请号：US16927513

申请日：2020-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato ,  Masayuki Sakakura

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/108

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

公开(公告)号：US10580798B2

公开(公告)日：2020-03-03

申请号：US15404771

申请日：2017-01-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato

IPC: H01L29/786 ,  H01L27/12 ,  G11C5/14 ,  G11C11/401 ,  H01L29/423 ,  G11C11/24 ,  H01L27/105 ,  H01L27/108 ,  H01L29/04 ,  H01L29/24 ,  H01L29/49 ,  H01L29/66 ,  G11C11/412 ,  G11C11/404 ,  H02M3/07

Abstract: A semiconductor device that can retain data for a long time is provided. The semiconductor device includes a first transistor and a second transistor. The first transistor contains an oxide semiconductor in a channel formation region. The second transistor includes a first gate and a second gate. A gate of the first transistor is connected to a first electrode of the first transistor. The first electrode of the first transistor is connected to the second gate. A negative potential is applied to a second electrode of the first transistor. The first electrode and the second electrode of the first transistor include a first end portion and a second end portion, respectively. The first end portion and the second end portion face each other. The first end portion includes a first arc and the second end portion includes a second arc when seen from the top. The radius of curvature of the second arc is larger than that of the first arc.

公开(公告)号：US10510757B2

公开(公告)日：2019-12-17

申请号：US15615873

申请日：2017-06-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/105 ,  H01L27/12 ,  H01L29/24 ,  H01L29/16 ,  G11C11/405 ,  G11C16/04 ,  H01L27/115 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/118 ,  H01L29/786 ,  H01L21/822 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78

Abstract: An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

公开(公告)号：US10411037B2

公开(公告)日：2019-09-10

申请号：US15198098

申请日：2016-06-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Kiyoshi Kato

IPC: H01L27/12 ,  G06K19/077 ,  G02F1/1333 ,  G02F1/1368 ,  G06K7/10 ,  H01L23/66 ,  H01L23/00 ,  H01L29/786

Abstract: It is an object of the present invention to provide a semiconductor device in which a sophisticated integrated circuit using a polycrystalline semiconductor is formed over a substrate which is weak with heat such as a plastic substrate or a plastic film substrate and a semiconductor device which transmits/receives power or a signal without wires, and a communication system thereof. One feature of the invention is that a semiconductor device, specifically, a processor, in which a sophisticated integrated circuit is fixed to a plastic substrate which is weak with heat by a stripping method such as a stress peel of process method to transmit/receive power or a signal without wires, for example, with an antenna or a light receiving element.

公开(公告)号：US10249347B2

公开(公告)日：2019-04-02

申请号：US14539067

申请日：2014-11-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kiyoshi Kato

IPC: G11C14/00 ,  G11C5/14 ,  G11C11/404 ,  G11C11/4074

Abstract: A normally-off state of an OS transistor is maintained or an on-state current thereof is increased without additionally generating a positive potential or a negative potential. When data is written to a node connecting an OS transistor and a capacitor, a potential supplied to the other side of the capacitor is set to an L level, and when the data is retained, the potential is switched from the L level to an H level. In addition, a power switch for a volatile memory circuit is provided on a low power supply potential side so that the supply of a power supply voltage can be stopped. Accordingly, at the time of data retention, a source and a drain of the OS transistor can be set at a high potential, whereby the normally-off state can be maintained and the on-state current can be increased.

公开(公告)号：US09991265B2

公开(公告)日：2018-06-05

申请号：US15157565

申请日：2016-05-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Kiyoshi Kato

IPC: H01L27/11 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  G11C13/00 ,  H01L49/02

CPC classification number: H01L27/1052 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L28/40 ,  H01L29/24 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object of one embodiment of the present invention is to provide a semiconductor device with a novel structure in which stored data can be stored even when power is not supplied in a data storing time and there is no limitation on the number of times of writing. The semiconductor device includes a first transistor which includes a first channel formation region using a semiconductor material other than an oxide semiconductor, a second transistor which includes a second channel formation region using an oxide semiconductor material, and a capacitor. One of a second source electrode and a second drain electrode of the second transistor is electrically connected to one electrode of the capacitor.

公开(公告)号：US20180026142A1

公开(公告)日：2018-01-25

申请号：US15678180

申请日：2017-08-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Jun Koyama

IPC: H01L29/786 ,  H01L23/66 ,  H04B1/40 ,  H01L27/12 ,  H01L29/10 ,  G06K19/077 ,  H01L27/06

CPC classification number: H01L29/78696 ,  G06K19/07749 ,  G06K19/07773 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1225 ,  H01L29/1033 ,  H01L29/7869 ,  H01L2223/6677 ,  H04B1/40 ,  Y02D70/00

Abstract: An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved in such a manner that a battery serving as a power supply source and a specific circuit are electrically connected to each other through a transistor in which a channel formation region is formed using an oxide semiconductor. The hydrogen concentration of the oxide semiconductor is lower than or equal to 5×1019 (atoms/cm3). Therefore, leakage current of the transistor can be reduced. As a result, power consumption of the semiconductor device in a standby state can be reduced. Further, the semiconductor device can have a long lifetime.

公开(公告)号：US09870816B2

公开(公告)日：2018-01-16

申请号：US14527310

申请日：2014-10-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato

IPC: G11C11/404 ,  G11C11/417 ,  G11C11/412 ,  H01L27/108 ,  G11C11/405

CPC classification number: G11C11/417 ,  G11C11/404 ,  G11C11/405 ,  G11C11/412 ,  H01L27/108

Abstract: A semiconductor device includes SRAM that stores data in an inverter loop including a CMOS inverter, transistors electrically connected to an input terminal or an output terminal of the CMOS inverter, and capacitors electrically connected to the corresponding transistors. The semiconductor device is configured to hold potentials corresponding to data at nodes between the transistors and the corresponding capacitors in a period during which supply of power to the CMOS inverter stops. In the period during which power supply stops, the potential of a wiring applying a low power supply potential is made equal to a high power supply potential to make the potentials of the input and output terminals of the CMOS inverter equal to the high power supply potential. The potentials corresponding to the data held at the nodes are applied to the input and output terminals of the CMOS inverter to restart power supply.

公开(公告)号：US09798178B2

公开(公告)日：2017-10-24

申请号：US15372831

申请日：2016-12-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kiyoshi Kato ,  Toshihiko Saito

IPC: G09G3/36 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1345 ,  G06F3/044 ,  G06F3/041 ,  H01L27/12

CPC classification number: G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

Abstract: A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

公开(公告)号：US09768210B2

公开(公告)日：2017-09-19

申请号：US15248167

申请日：2016-08-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tamae Takano ,  Nobuharu Ohsawa ,  Kiyoshi Kato

IPC: H01L27/13 ,  H01L33/36 ,  H01L51/50 ,  H01L51/52 ,  H01L23/522 ,  H01L27/06 ,  H01L27/12 ,  H01Q1/22 ,  H01Q9/27 ,  H01L51/05 ,  H01L23/498 ,  H01L23/66 ,  G06K19/077 ,  G11C7/06 ,  G11C7/22 ,  H01L27/28 ,  H01Q1/36 ,  H01F5/00

CPC classification number: H01L27/13 ,  G06K19/07784 ,  G11C7/062 ,  G11C7/22 ,  H01F5/003 ,  H01L23/49838 ,  H01L23/5227 ,  H01L23/66 ,  H01L27/0688 ,  H01L27/1203 ,  H01L27/1214 ,  H01L27/1255 ,  H01L27/285 ,  H01L33/36 ,  H01L51/05 ,  H01L51/0591 ,  H01L51/5012 ,  H01L51/5203 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01Q1/2283 ,  H01Q1/36 ,  H01Q9/27 ,  Y10S257/922 ,  H01L2924/00

Abstract: When a conductive layer occupying a large area is provided in a coiled antenna portion, it has been difficult to supply power stably. A memory circuit portion and a coiled antenna portion are disposed by being stacked together; therefore, it is possible to prevent a current from flowing through a conductive layer occupying a large area included in the memory circuit portion, and thus, power saving can be achieved. In addition, the memory circuit portion and the coiled antenna portion are disposed by being stacked together, and thus, it is possible to use a space efficiently. Therefore, downsizing can be realized.