公开(公告)号：US20160239233A1

公开(公告)日：2016-08-18

申请号：US15137802

申请日：2016-04-25

Applicant: Inphi Corporation

Inventor： Christopher Haywood

IPC: G06F3/06 ,  G11C14/00 ,  G11C7/10 ,  G06F13/42

CPC classification number: G06F3/0626 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/06 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C14/0045

Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.

公开(公告)号：US20160191151A1

公开(公告)日：2016-06-30

申请号：US15065789

申请日：2016-03-09

Applicant: INPHI CORPORATION

Inventor： Radhakrishnan L. NAGARAJAN

IPC: H04B10/038

CPC classification number: H04B10/038 ,  H01S5/0085 ,  H01S5/06825 ,  H01S5/4025 ,  H04B10/503 ,  H04B10/516 ,  H04B10/801 ,  H04J14/02 ,  H04L1/0042 ,  H04Q11/0003

Abstract: In an example, the present invention includes an integrated system on chip device. At least a pair of laser devices are associated with a channel and coupled to a switch to select one of the pair of laser devices to be coupled to an optical multiplexer to provide for a redundant laser device.

Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 至少一对激光器件与通道相关联并耦合到开关，以选择要耦合到光复用器的一对激光器件中的一个以提供冗余激光器件。

公开(公告)号：US09331706B1

公开(公告)日：2016-05-03

申请号：US14511074

申请日：2014-10-09

Applicant: INPHI CORPORATION

Inventor： Mohammad Ranjbar

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/0609 ,  H03M1/002 ,  H03M1/1215 ,  H03M1/145 ,  H03M1/365 ,  H03M1/466

Abstract: The present invention is directed to signal processing systems and methods thereof. In various embodiments, the present invention provides an analog-to-digital conversion (ADC) system that includes a flash ADC portion and a time-interleaved parallel SAR portion. For an n-bit ADC process, the flash ADC portion converts k MSBs of the n bits during a single cycle, and the SAR portion converts n−k LSBs in m number of cycles. The SAR portion includes a number of SAR channels that perform A/D conversion in parallel, and the k MSB from the course flash converter is verified for errors by the SAR portion and allows a net saving of the power consumption by reducing the number of fine resolution SARs. There are other embodiments as well.

Abstract translation: 本发明涉及信号处理系统及其方法。 在各种实施例中，本发明提供一种模数转换（ADC）系统，其包括闪存ADC部分和时间交织的并行SAR部分。 对于n位ADC处理，闪速ADC部分在单个周期内转换n个位的k个MSB，并且SAR部分以m个周期数转换n-k个LSB。 SAR部分包括并行执行A / D转换的多个SAR信道，并且通过SAR部分验证来自过程闪存转换器的k个MSB的误差，并且通过减少精细数量来节省功耗的净节省 分辨率SAR。 还有其它实施例。

公开(公告)号：US09325419B1

公开(公告)日：2016-04-26

申请号：US14536294

申请日：2014-11-07

Applicant: INPHI CORPORATION

Inventor： Masaki Kato

IPC: H04B10/00 ,  H04B10/40 ,  H04J14/02 ,  H04B10/43

CPC classification number: H04B10/43 ,  H04B10/40 ,  H04B10/506 ,  H04B10/676 ,  H04J14/02

Abstract: Method and devices of controlling wavelengths in two-channel DEMUX/MUX in silicon photonics are provided. The two-channel DEMUX/MUX includes a waveguide-based delay-line-interferometer at least in receiver portion of a two-channel transceiver for DWDM optical transmission loop and is configured to split a light wave with combined two-wavelengths into one light wave with locked one channel wavelength and another light wave with locked another channel wavelength. The waveguide-based delayed-line interferometer (DLI) is characterized by a free-spectral-range configured to be equal to twice of channel spacing. The method includes tuning heater of DLI in receiver of each two-channel transceiver by using either low-frequency dither signals added on MZMs associated with respective two channels as feedback signal or one DFB laser wavelength tapped from an input of transmitter portion at one channel before or after the MZMs as a direct wavelength reference to feed into an output of receiver portion at another channel.

Abstract translation: 提供了在硅光子学中控制双通道DEMUX / MUX中的波长的方法和装置。 双通道DEMUX / MUX至少在用于DWDM光传输环路的双通道收发器的接收器部分中包括基于波导的延迟线干涉仪，并且被配置为将具有组合的两个波长的光波分成一个光波 锁定一个信道波长，另一个光波锁定另一个信道波长。 基于波导的延迟线干涉仪（DLI）的特征在于被配置为等于信道间隔的两倍的自由谱范围。 该方法包括通过使用与相应的两个通道相关联的MZM上添加的低频抖动信号作为反馈信号或者在一个通道的发射器部分的输入端抽头的一个DFB激光波长，在每个双通道收发器的接收机中调谐DLI的加热器。 或在MZM之后作为直接波长参考，以在另一个通道上馈送到接收器部分的输出。

公开(公告)号：US20160026601A1

公开(公告)日：2016-01-28

申请号：US14878680

申请日：2015-10-08

Applicant: INPHI CORPORATION

Inventor： Christopher HAYWOOD ,  Chao XU ,  Fouad G. TAMER

IPC: G06F13/42 ,  H05K7/20 ,  H05K7/14

CPC classification number: G06F13/28 ,  G06F13/4027 ,  G06F13/4282 ,  G11C8/00 ,  H05K7/1487 ,  H05K7/1488 ,  H05K7/1489 ,  H05K7/1491 ,  H05K7/1492 ,  H05K7/20836 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention is directed to server systems and methods thereof. More specifically, embodiments of the present invention provides a memory controller within a server system, where the memory controller is disengageably connected to one or more processors, a plurality of volatile memory modules, and plurality of solid-state memory modules. This memory controller may be connected to other similarly configured memory controllers. The volatile and solid-state memory modules can be removed and/or replaced. There are other embodiments as well.

公开(公告)号：US09230635B1

公开(公告)日：2016-01-05

申请号：US13787350

申请日：2013-03-06

Applicant: Inphi Corporation

Inventor： David T. Wang ,  Andrew Burstein

IPC: G06F12/02 ,  G11C11/406 ,  G06F11/22

CPC classification number: G11C11/40607 ,  G06F11/22 ,  G06F12/0246 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40622 ,  G11C29/50016 ,  G11C2211/4061

Abstract: A method for manufacturing a dynamic random access memory device is provided. The method includes fabricating a dynamic random access memory device having a plurality of memory cells. Each of the memory cells has a refresh characteristic that meets or exceeds a refresh specification provided for a DDR3 SDRAM device or a DDR4 SDRAM device. The method includes testing the dynamic random access memory device. The testing includes determining the refresh characteristic for each of the memory cells, classifying each of the memory cells as a good memory cell or a bad memory cell based upon the refresh characteristic, identifying each of the bad memory cells, and storing an address location for each of the bad memory cells. The method then includes transferring the address location for each of the bad memory cells into an address match table.

Abstract translation: 提供了一种用于制造动态随机存取存储器件的方法。 该方法包括制造具有多个存储单元的动态随机存取存储器件。 每个存储单元具有满足或超过为DDR3 SDRAM设备或DDR4 SDRAM设备提供的刷新规范的刷新特性。 该方法包括测试动态随机存取存储器件。 测试包括确定每个存储器单元的刷新特性，基于刷新特性将每个存储单元分类为好的存储器单元或坏存储器单元，识别每个坏存储器单元，以及存储用于 每个坏记忆体单元。 该方法然后包括将每个坏存储器单元的地址位置传送到地址匹配表中。

公开(公告)号：US09225560B1

公开(公告)日：2015-12-29

申请号：US14681989

申请日：2015-04-08

Applicant: INPHI CORPORATION

Inventor： Parmanand Mishra ,  Michael S. Harwood

IPC: H04L25/06 ,  H04L25/10 ,  H04L25/03 ,  H03K17/687

CPC classification number: H04L25/03885 ,  H03K17/687 ,  H04B10/58 ,  H04B10/6163 ,  H04L25/03019

Abstract: The present invention is directed to data communication systems and methods. In various embodiments, the present invention provides a CML device that changes output frequency response by varying resistance values of its load resistance and source resistance. A bias control voltage is used to adjust the tail current of the CML device, and the tail current adjusts the output gain of the CML device. There are other embodiments as well.

Abstract translation: 本发明涉及数据通信系统和方法。 在各种实施例中，本发明提供一种通过改变其负载电阻和源极电阻的电阻值来改变输出频率响应的CML器件。 使用偏置控制电压来调整CML器件的尾部电流，尾电流调节CML器件的输出增益。 还有其它实施例。

公开(公告)号：US09209962B1

公开(公告)日：2015-12-08

申请号：US14715494

申请日：2015-05-18

Applicant: Inphi Corporation

Inventor： Parmanand Mishra ,  Simon Forey

IPC: H04L7/00 ,  H04L7/033 ,  H04B1/10

CPC classification number: H04L7/0079 ,  H03K5/135 ,  H03K2005/00052 ,  H03L7/0807 ,  H04B1/10 ,  H04B1/40 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/06 ,  H04L7/10

Abstract: The present invention is directed to data communication. More specifically, the present invention provides a mechanism for determining an adjustment delay that minimizes skew error due to poor alignment between edge samples and data samples. The adjustment delay is determined by sampling edge samples and data samples using different test delays at a calibration frequency that is different from the sampling frequency. The test delay associated with the least average position between the data samples and edge samples is selected as the adjustment delay. The adjustment delay is used as a parameter when sampling data at the sampling frequency. There are other embodiments as well.

Abstract translation: 本发明涉及数据通信。 更具体地，本发明提供了一种用于确定最小化由于边缘样本和数据样本之间的不良对准导致的偏斜误差的调整延迟的机制。 调整延迟由采样边缘样本和采样频率不同的不同测试延迟采样数据样本确定。 选择与数据样本和边缘样本之间的最小平均位置相关联的测试延迟作为调整延迟。 当以采样频率采样数据时，调整延迟用作参数。 还有其它实施例。

公开(公告)号：US20150261442A1

公开(公告)日：2015-09-17

申请号：US14665968

申请日：2015-03-23

Applicant: INPHI CORPORATION

Inventor： CHRISTOPHER HAYWOOD

IPC: G06F3/06 ,  G11C7/10 ,  G06F13/16

CPC classification number: G06F3/0626 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0685 ,  G06F3/0688 ,  G06F12/06 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/1694 ,  G06F13/4282 ,  G11C7/1072 ,  G11C14/0045

Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The memory buffer may be employed in various types of systems, such as a computer server system, a network system, or a data center.

Abstract translation: 本存储器系统包括存储器缓冲器，其具有被布置为缓冲由主机控制器写入或存储在DIMM上的RAM芯片的数据和/或命令字节的接口。 存储器缓冲器还包括至少一个额外的接口，其布置成在主机控制器或RAM芯片与耦合到至少一个附加接口的一个或多个外部设备之间缓冲数据和/或命令字节。 例如，存储器缓冲器可以包括SATA接口，并且被布置成在主机控制器或RAM芯片与耦合到SATA接口的闪存设备之间传送数据。 存储器缓冲器可以用于各种类型的系统，例如计算机服务器系统，网络系统或数据中心。

公开(公告)号：US20150249501A1

公开(公告)日：2015-09-03

申请号：US14625489

申请日：2015-02-18

Applicant: INPHI CORPORATION

Inventor： Radhakrishnan L. NAGARAJAN

IPC: H04B10/2575 ,  H04B10/40 ,  H04J14/02

CPC classification number: H04J14/02 ,  H04B10/40

Abstract: An integrated apparatus with optical/electrical interfaces and protocol converter on a single silicon substrate. The apparatus includes an optical module comprising one or more modulators respectively coupled with one or more laser devices for producing a first optical signal to an optical interface and one or more photodetectors for detecting a second optical signal from the optical interface to generate a current signal. Additionally, the apparatus includes a transmit lane module coupled between the optical module and an electrical interface to receive a first electric signal from the electrical interface and provide a framing protocol for driving the one or more modulators. Furthermore, the apparatus includes a receive lane module coupled between the optical module and the electrical interface to process the current signal to send a second electric signal to the electrical interface.

Abstract translation: 在单个硅衬底上具有光/电接口和协议转换器的集成设备。 该装置包括一个光学模块，该光学模块包括分别与一个或多个激光装置耦合的一个或多个调制器，用于产生到光学接口的第一光信号，以及一个或多个光电检测器，用于检测来自光学接口的第二光信号以产生电流信号。 另外，该装置包括耦合在光学模块和电接口之间以从电接口接收第一电信号并提供用于驱动一个或多个调制器的成帧协议的发射通道模块。 此外，该装置包括耦合在光学模块和电接口之间的接收通道模块，以处理电流信号以向电接口发送第二电信号。