公开(公告)号：US09142318B2

公开(公告)日：2015-09-22

申请号：US13887167

申请日：2013-05-03

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Joel Damiens ,  Elise Leroux

IPC: G11C17/16 ,  G11C17/18 ,  H01L27/112 ,  H01L27/10

CPC classification number: G11C17/165 ,  G11C17/18 ,  H01L27/101 ,  H01L27/11206

Abstract: A method for controlling the breakdown of an antifuse memory cell formed on a semiconductor substrate, including the steps of: applying a programming voltage; detecting a breakdown time; and interrupting the application of the programming voltage at a time following the breakdown time by a post-breakdown time.

Abstract translation: 一种用于控制形成在半导体衬底上的反熔层存储单元击穿的方法，包括以下步骤：施加编程电压; 检测故障时间; 并且在故障时间之后的故障时间之后中断施加编程电压。

公开(公告)号：US09136366B2

公开(公告)日：2015-09-15

申请号：US14156559

申请日：2014-01-16

Applicant: Commissariat a l'energie atomique et aux energies alternatives ,  STMicroelectronics SA

Inventor： Bastien Giraud ,  Jean-Philippe Noel ,  Maud Vinet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/772 ,  H01L29/786

CPC classification number: H01L29/78 ,  H01L29/42392 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78696

Abstract: An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.

Abstract translation: 集成电路包括硅衬底，衬底上方的接地平面，接地平面上方的掩埋绝缘体层，掩埋绝缘体层上方的硅层，并由掩埋绝缘体层与接地层分离，以及FDSOI晶体管。 晶体管具有适于在硅层中形成的沟道，硅层中和/或硅层上的源极和漏极，以及覆盖沟道的上表面的栅极，并且具有覆盖沟道的侧面的侧面部分，以及 在地面以上。 横向部分和接地面之间的距离不大于接地平面和硅层之间的掩埋绝缘体层的厚度的三纳米至少五倍。 接地层由掩埋绝缘体层与栅极分离。

公开(公告)号：US09124293B2

公开(公告)日：2015-09-01

申请号：US13914145

申请日：2013-06-10

Applicant: STMicroelectronics SA

Inventor： Didier Belot ,  Jean-Baptiste Begueret ,  Yann Deval ,  Dominique Dallet ,  André Mariano

IPC: H03M3/00

CPC classification number: H03M3/458 ,  H03M3/402 ,  H03M3/484 ,  H03M3/50

Abstract: Continuous time analog/digital converter, comprising a sigma delta modulator (MSD1) configured to receive an analog input signal (x(t)) and comprising high-pass filtering means (MF) the chopping frequency of which is equal to half of the sampling frequency (Fs) of the quantization means (QTZ) of the modulator (MSD1).

Abstract translation: 连续时间模拟/数字转换器，包括被配置为接收模拟输入信号（x（t））并且包括其斩波频率等于采样的一半的高通滤波装置（MF）的Σ-Δ调制器（MSD1） 调制器（MSD1）的量化装置（QTZ）的频率（Fs）。

公开(公告)号：US20150137133A1

公开(公告)日：2015-05-21

申请号：US14537992

申请日：2014-11-11

Applicant: STMicroelectronics SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Michel Marty ,  Francois Roy

IPC: H01L21/02 ,  H01L31/0232 ,  H01L31/0376

CPC classification number: H01L21/02675 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/268 ,  H01L27/1464 ,  H01L27/14698 ,  H01L31/02327 ,  H01L31/03762 ,  H01L31/1872 ,  Y02E10/548 ,  Y02P70/521

Abstract: A method of forming a heavily-doped silicon layer on a more lightly-doped silicon substrate including the steps of depositing a heavily-doped amorphous silicon layer; depositing a silicon nitride layer; and heating the amorphous silicon layer to a temperature higher than or equal to the melting temperature of silicon.

Abstract translation: 一种在更轻掺杂的硅衬底上形成重掺杂硅层的方法，包括沉积重掺杂非晶硅层的步骤; 沉积氮化硅层; 并将非晶硅层加热到高于或等于硅的熔融温度的温度。

公开(公告)号：US20150118805A1

公开(公告)日：2015-04-30

申请号：US14526081

申请日：2014-10-28

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics, Inc.

Inventor： Denis Rideau ,  Elise Baylac ,  Emmanuel Josse ,  Pierre Morin ,  Olivier Nier

IPC: H01L21/8234 ,  H01L21/324 ,  H01L29/78 ,  H01L21/265 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L21/823481 ,  H01L21/02356 ,  H01L21/02532 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76237 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1203 ,  H01L29/7831 ,  H01L29/7846 ,  H01L29/7847

Abstract: The invention concerns a method of forming a semiconductor layer having uniaxial stress including: forming, in a semiconductor structure having a stressed semiconductor layer, one or more first isolation trenches in a first direction for delimiting a first dimension of at least one transistor to be formed in said semiconductor structure; forming, in the semiconductor structure, one or more second isolation trenches in a second direction for delimiting a second dimension of the at least one transistor, the first and second isolation trenches being at least partially filled with an insulating material; and before or after the formation of the second isolation trenches, decreasing the viscosity of the insulating material in the first isolation trenches by implanting atoms of a first material into the first isolation trenches, wherein atoms of the first material are not implanted into the second isolation trenches.

Abstract translation: 本发明涉及一种形成具有单轴应力的半导体层的方法，包括：在具有应力半导体层的半导体结构中形成在第一方向上的一个或多个第一隔离沟槽，以限定待形成的至少一个晶体管的第一维度 在所述半导体结构中; 在所述半导体结构中，在第二方向上形成用于限定所述至少一个晶体管的第二尺寸的一个或多个第二隔离沟槽，所述第一和第二隔离沟槽至少部分地填充有绝缘材料; 并且在形成第二隔离沟槽之前或之后，通过将第一材料的原子注入到第一隔离沟槽中来降低第一隔离沟槽中的绝缘材料的粘度，其中第一材料的原子未被注入第二隔离层 沟渠

公开(公告)号：US20150113247A1

公开(公告)日：2015-04-23

申请号：US14511843

申请日：2014-10-10

Applicant: STMicroelectronics SA

Inventor： Philippe Escalona

IPC: G06F9/30 ,  G06F15/76

CPC classification number: G06F15/76 ,  G06F9/30156 ,  G06F21/00 ,  G06F21/75

Abstract: A method for securing a data processing system having a processing unit is disclosed. At least a group of N1 digital words of m1 bits is selected from among the set of M1 digital words. N1 is less than M1. These words are selected in such a way that each selected digital word differs from all the other selected digital words by a number of bits at least equal to an integer p which is at least equal to 2. The group of N1 digital words of m1 bits form at least one group of N1 executable digital instructions. The processing unit is configured to make it capable of executing each instruction of the at least one group of N1 executable digital instructions.

Abstract translation: 公开了一种用于确保具有处理单元的数据处理系统的方法。 从一组M1数字字中选择至少一组m1位的N1个数字字。 N1小于M1。 这些字被选择为使得每个所选数字字与所有其它所选择的数字字不同，至少等于至少等于2的整数p的位数。m1位的N1个数字字组 形成至少一组N1可执行数字指令。 处理单元被配置为使得能够执行至少一组N1可执行数字指令的每个指令。

公开(公告)号：US08994416B2

公开(公告)日：2015-03-31

申请号：US14045642

申请日：2013-10-03

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: H03B19/00 ,  H03K3/02 ,  H03K3/037

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US20150085560A1

公开(公告)日：2015-03-26

申请号：US14494383

申请日：2014-09-23

Applicant: STMicroelectronics SA

Inventor： Philippe Candelier ,  Thérèse Andrée Diokh ,  Joel Damiens ,  Elise Le Roux

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/004 ,  G11C14/009 ,  G11C2013/0071 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2013/009 ,  G11C2213/79

Abstract: A method of controlling an array of ReRAM cells including programmable-resistance storage elements, including: during a standby period, applying a non-zero standby voltage between electrodes of the storage elements of each cell of the array.

Abstract translation: 一种控制包括可编程电阻存储元件的ReRAM单元阵列的方法，包括：在待机期间，在阵列的每个单元的存储元件的电极之间施加非零备用电压。

公开(公告)号：US20150083894A1

公开(公告)日：2015-03-26

申请号：US14557158

申请日：2014-12-01

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA

Inventor： David Coulon ,  Benoit Deschamps ,  Frederic Barbier

IPC: H04N5/345 ,  H01L27/146 ,  H04N5/378

CPC classification number: H04N5/345 ,  H01L27/14605 ,  H01L27/14647 ,  H01L27/14689 ,  H04N5/378

Abstract: An imaging device includes at least one photosite formed in a semiconducting substrate and fitted with a filtering device for filtering at least one undesired radiation. The filtering device is buried in the semiconducting substrate at a depth depending on the wavelength of the undesired radiation.

Abstract translation: 成像装置包括在半导体衬底中形成的至少一个光电子，并装配有用于过滤至少一个不需要的辐射的过滤装置。 过滤装置以取决于不需要的辐射的波长的深度埋在半导体衬底中。

公开(公告)号：US08988570B2

公开(公告)日：2015-03-24

申请号：US13711037

申请日：2012-12-11

Applicant: STMicroelectronics SA

Inventor： Frederic Barbier

IPC: H04N5/3745 ,  H04N5/335 ,  H04N3/14 ,  H04N5/353 ,  H04N5/355 ,  H01L27/146

CPC classification number: H04N5/335 ,  H01L27/14641 ,  H04N3/155 ,  H04N5/347 ,  H04N5/3532 ,  H04N5/3559 ,  H04N5/374 ,  H04N5/37452

Abstract: A method may include a cycle of reading a current pixel including connecting the capacitive node of the pixel to a capacitive node of a previous pixel already read, connecting the capacitive node of the current pixel and the capacitive node of a previous pixel to an output line, reading a first voltage of the capacitive node of the pixel through the output line, transferring charges from the accumulation node to the capacitive node of the pixel, reading a second voltage of the capacitive node of the pixel through the output line, and disconnecting the capacitive node from the capacitive node of a previous pixel, and a cycle of reading a next pixel. This cycle may include accumulating charges in the accumulation node of the next pixel while the capacitive node of the current pixel is connected to a capacitive node of a previous pixel.

Abstract translation: 方法可以包括读取当前像素的循环，包括将像素的电容性节点连接到已经读取的先前像素的电容性节点，将当前像素的电容性节点和先前像素的电容性节点连接到输出线 通过输出线读取像素的电容性节点的第一电压，将电荷从累积节点传送到像素的电容性节点，通过输出线读取像素的电容性节点的第二电压，并且断开 来自先前像素的电容性节点的电容性节点以及读取下一个像素的周期。 该周期可以包括在下一个像素的累积节点中积累电荷，而当前像素的电容节点连接到先前像素的电容节点。