VERTICAL ACCESS DEVICES, SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED METHODS
    131.
    发明申请
    VERTICAL ACCESS DEVICES, SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED METHODS 有权
    垂直存取设备,半导体器件结构和相关方法

    公开(公告)号:US20150243748A1

    公开(公告)日:2015-08-27

    申请号:US14190807

    申请日:2014-02-26

    Abstract: A vertical access device comprises a semiconductive base comprising a first source/drain region, a semiconductive pillar extending vertically from the semiconductive base, and a gate electrode adjacent a sidewall of the semiconductive pillar. The semiconductive pillar comprises a channel region overlying the first source/drain region, and a second source/drain region overlying the channel region. An opposing sidewall of the semiconductive pillar is not adjacent the gate electrode or another gate electrode. Semiconductive device structures, methods of forming a vertical access device, and methods of forming a semiconductive structure are also described.

    Abstract translation: 垂直存取装置包括半导体基底,其包括第一源极/漏极区域,从半导体基底垂直延伸的半导体柱和邻近半导体支柱的侧壁的栅电极。 半导体柱包括覆盖第一源极/漏极区域的沟道区域和覆盖沟道区域的第二源极/漏极区域。 半导体柱的相对的侧壁不与栅电极或另一栅电极相邻。 还描述了半导体器件结构,形成垂直访问器件的方法以及形成半导体结构的方法。

    Floating Body Transistor Constructions, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions
    133.
    发明申请
    Floating Body Transistor Constructions, Semiconductor Constructions, and Methods of Forming Semiconductor Constructions 审中-公开
    浮体晶体管结构,半导体结构和形成半导体结构的方法

    公开(公告)号:US20150145044A1

    公开(公告)日:2015-05-28

    申请号:US14603223

    申请日:2015-01-22

    Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.

    Abstract translation: 本发明包括含有U形半导体材料片的浮体晶体管结构。 U形有一对连接到中心部分的插脚。 每个插脚包含一对门控耦合的源极/漏极区域的源极/漏极区域,并且晶体管的浮体在中心部分内。 半导体材料切片可以位于前门和后门之间。 可以将浮体晶体管结构并入到存储器阵列中,这又可以并入到电子系统中。 本发明还包括形成浮体晶体管结构的方法,以及将浮体晶体管结构结合到存储器阵列中的方法。

    Arrays of vertically stacked tiers of non-volatile cross point memory cells
    134.
    发明授权
    Arrays of vertically stacked tiers of non-volatile cross point memory cells 有权
    垂直堆叠的非易失性交叉点存储单元阵列

    公开(公告)号:US09036402B2

    公开(公告)日:2015-05-19

    申请号:US14255283

    申请日:2014-04-17

    Abstract: An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

    Abstract translation: 垂直堆叠层的非易失性交叉点存储单元的阵列包括在存储单元的各个层内的多个水平取向的字线。 具有局部垂直位线延伸的多个水平定向的全局位线延伸穿过多个层。 存储单元的个体包括在水平定向的字线之一和本地垂直位线延伸之一中的一个之间接收的多电阻状态材料,其中这些交叉具有这样的交叉的单个存储器单元的相对的导电电极。 多个位线选择电路单独地电和物理地连接到本地垂直位线延伸的个体,并且被配置为向全局水平位线的个体提供电压电位。 公开了其它实施例和方面。

    Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells
    135.
    发明申请
    Stack Of Horizontally Extending And Vertically Overlapping Features, Methods Of Forming Circuitry Components, And Methods Of Forming An Array Of Memory Cells 有权
    堆叠的水平扩展和垂直重叠特征,形成电路组件的方法和形成记忆单元阵列的方法

    公开(公告)号:US20150129935A1

    公开(公告)日:2015-05-14

    申请号:US14602559

    申请日:2015-01-22

    Abstract: A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion and an end portion. At least some of the features extend farther in the horizontal direction in the end portion moving deeper into the stack in the end portion. Operative structures are formed vertically through the features in the primary portion and dummy structures are formed vertically through the features in the end portion. Horizontally elongated openings are formed through the features to form horizontally elongated and vertically overlapping lines from material of the features. The lines individually extend from the primary portion into the end portion, and individually laterally about sides of vertically extending portions of both the operative structures and the dummy structures. Sacrificial material that is elevationally between the lines is at least partially removed in the primary and end portions laterally between the horizontally elongated openings. Other aspects and implementations are disclosed.

    Abstract translation: 形成电路部件的方法包括形成水平延伸和垂直重叠特征的堆叠。 堆叠具有主要部分和端部。 至少一些特征在末端部分中更深地移动到堆叠中的端部中在水平方向上延伸得更远。 操作结构通过主要部分的特征垂直地形成,并且虚拟结构通过端部中的特征垂直地形成。 通过特征形成水平细长的开口以从特征的材料形成水平细长的和垂直重叠的线。 这些线分别从主要部分延伸到端部,并且单独地横向地围绕操作结构和虚拟结构的垂直延伸部分的侧面。 至少部分地,在水平伸长的开口之间的主要端部和端部中部分地去除在线之间高度的牺牲材料。 公开了其他方面和实现。

    Methods of forming field effect transistors on substrates
    137.
    发明授权
    Methods of forming field effect transistors on substrates 有权
    在衬底上形成场效应晶体管的方法

    公开(公告)号:US08877589B2

    公开(公告)日:2014-11-04

    申请号:US13865117

    申请日:2013-04-17

    Abstract: The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

    Abstract translation: 本发明包括形成场效应晶体管的方法。 在一个实施方案中,本发明包括在衬底上形成场效应晶体管的方法,其中场效应晶体管包括一对导电掺杂的源极/漏极区域,在该对源极/漏极区域之间接收的沟道区域,以及 晶体管栅极可靠地接收在沟道区域。 这种实现包括在沉积材料之前对该对源极/漏极区进行掺杂剂激活退火,从而制造晶体管栅极的导电部分。 考虑了其他方面和实现。

    Dual Work Function Recessed Access Device and Methods of Forming
    139.
    发明申请
    Dual Work Function Recessed Access Device and Methods of Forming 有权
    双功能嵌入式接入设备及其形成方法

    公开(公告)号:US20140197484A1

    公开(公告)日:2014-07-17

    申请号:US14217844

    申请日:2014-03-18

    CPC classification number: H01L29/7827 H01L29/42376 H01L29/4966 H01L29/66621

    Abstract: A recessed access device having a gate electrode formed of two or more gate materials having different work functions may reduce the gate-induced drain leakage current losses from the recessed access device. The gate electrode may include a first gate material having a high work function disposed in a bottom portion of the recessed access device and a second gate material having a lower work function disposed over the first gate material and in an upper portion of the recessed access device.

    Abstract translation: 具有由具有不同功函数的两个或多个栅极材料形成的栅电极的凹陷存取装置可以减小来自凹陷存取装置的栅极引起的漏极漏电流损耗。 栅电极可以包括具有设置在凹陷入口装置的底部中的高功函的第一栅极材料和具有设置在第一栅极材料上的下功函数的第二栅极材料以及凹陷入口装置的上部 。

    Apparatus relating to a memory cell having a floating body
    140.
    发明授权
    Apparatus relating to a memory cell having a floating body 有权
    涉及具有浮体的存储单元的装置

    公开(公告)号:US08767457B2

    公开(公告)日:2014-07-01

    申请号:US14043476

    申请日:2013-10-01

    CPC classification number: H01L27/10802 H01L27/1203 H01L29/66833 H01L29/7841

    Abstract: An apparatus is disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer, the transistor including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell may include a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

    Abstract translation: 公开了一种具有浮体的存储单元的装置。 存储单元可以包括绝缘层上的晶体管,晶体管包括源极和漏极。 存储单元还可以包括浮动体,其包括位于源极和漏极之间的第一区域,远离源极和漏极中的每一个定位的第二区域,以及延伸穿过绝缘层并且将第一区域耦合到第二区域的第二区域 地区。 另外,存储单元可以包括至少部分地围绕第二区域并被配置为可操作地耦合到偏置电压的偏置栅极。 此外,存储单元可以包括多个电介质层,其中第二区域的每个外部垂直表面具有与其相邻的多个电介质层。

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