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    Buffer circuit with adaptive repair capability
    131.
    发明授权
    Buffer circuit with adaptive repair capability 有权

    公开(公告)号：US12040035B2

    公开(公告)日：2024-07-16

    申请号：US18233257

    申请日：2023-08-11

    Applicant: Rambus Inc.

    Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

    IPC: G11C29/00 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/44 ,  G11C29/52

    CPC classification number: G11C29/4401 ,  G11C5/04 ,  G11C11/401 ,  G11C29/022 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/88 ,  G11C2029/4402

    Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

    Energy efficient storage of error-correction-detection information
    132.
    发明授权
    Energy efficient storage of error-correction-detection information 有权

    公开(公告)号：US12001283B2

    公开(公告)日：2024-06-04

    申请号：US18130810

    申请日：2023-04-04

    Applicant: Rambus Inc.

    Inventor： Michael Raymond Miller ,  Stephen Magee ,  John Eric Linstadt

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  G06F11/1048

    Abstract: Data and error correction information may involve accessing multiple data channels (e.g., 8) and one error detection and correction channel concurrently. This technique requires a total of N+1 row requests for each access, where N is the number of data channels (e.g., 8 data row accesses and 1 error detection and correction row access equals 9 row accesses.) A single (or at least less than N) data channel row may be accessed concurrently with a single error detection and correction row. This reduces the number of row requests to two (2)—one for the data and one for the error detection and correction information. Because, row requests consume power, reducing the number of row requests is more power efficient.

    Data-buffer component with variable-width data ranks and configurable data-rank timing
    136.
    发明授权
    Data-buffer component with variable-width data ranks and configurable data-rank timing 有权

    公开(公告)号：US11809345B2

    公开(公告)日：2023-11-07

    申请号：US17677714

    申请日：2022-02-22

    Applicant: Rambus Inc.

    Inventor： Thomas J. Giovannini ,  John Eric Linstadt ,  Catherine Chen

    IPC: G06F13/16 ,  G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/1689 ,  G06F13/1673 ,  G06F13/1678 ,  G06F13/4022 ,  G06F13/4265

    Abstract: A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.

    Dual-domain combinational logic circuitry
    139.
    发明授权
    Dual-domain combinational logic circuitry 有权

    公开(公告)号：US11481192B1

    公开(公告)日：2022-10-25

    申请号：US17363940

    申请日：2021-06-30

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  John Eric Linstadt

    IPC: G06F7/503 ,  G06F7/502 ,  H03K19/0185 ,  G06F9/30 ,  H03K19/00

    Abstract: A combinational logic circuit includes input circuitry to receive a first and second input signals that transition between supply voltages of first and second voltage domain, respectively. The input circuitry generates, based on the first and second input signals, a first internal signal that transitions between one of the supply voltages of the first voltage domain and one of the supply voltages of the second voltage domain. Output circuitry within the combinational logic circuit generates an output signal that transitions between the upper and lower supply voltages of the first voltage domain in response to transition of the first internal signal.

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