公开(公告)号：USRE50124E1

公开(公告)日：2024-09-10

申请号：US17470119

申请日：2021-09-09

Applicant: Mosaid Technologies Incorporated

Inventor： Hyoung Seub Rhie

IPC: H01L27/115 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  H01L29/792 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  H01L29/7926 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional integrated circuit non-volatile memory array includes a memory array of vertical channel NAND flash strings connected between a substrate source line and upper layer connection lines which each include n-type drain regions and p-type body line contact regions alternately disposed on each side of undoped or lightly doped string body regions so that each NAND flash string includes a vertical string body portion connected to a horizontal string body portion formed from the string body regions of the upper body connection lines.

公开(公告)号：US11880569B2

公开(公告)日：2024-01-23

申请号：US18303127

申请日：2023-04-19

Applicant: Mosaid Technologies Incorporated

Inventor： Peter B. Gillingham ,  Graham Allan

IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00 ,  H03K5/00

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/00

Abstract: A clock mode configuration circuit for a memory device. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

公开(公告)号：US11669248B2

公开(公告)日：2023-06-06

申请号：US17731408

申请日：2022-04-28

Applicant: Mosaid Technologies Incorporated

Inventor： Peter B. Gillingham ,  Graham Allan

IPC: G11C8/00 ,  G06F3/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  G11C16/04 ,  G11C14/00 ,  H03K5/00

CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F13/1694 ,  G11C7/1045 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C14/0018 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/28 ,  G11C16/32 ,  H03K2005/00247 ,  Y02D10/00

Abstract: A clock mode configuration circuit for a memory device is described. A memory system includes any number of memory devices serially connected to each other, where each memory device receives a clock signal. The clock signal can be provided either in parallel to all the memory devices or serially from memory device to memory device through a common clock input. The clock mode configuration circuit in each memory device is set to a parallel mode for receiving the parallel clock signal, and to a serial mode for receiving a source synchronous clock signal from a prior memory device. Depending on the set operating mode, the data input circuits will be configured for the corresponding data signal format, and the corresponding clock input circuits will be either enabled or disabled. The parallel mode and the serial mode is set by sensing a voltage level of a reference voltage provided to each memory device.

公开(公告)号：US11664463B2

公开(公告)日：2023-05-30

申请号：US17369007

申请日：2021-07-07

Applicant: Mosaid Technologies Incorporated

Inventor： Hyoung Seub Rhie

IPC: H01L29/792 ,  H01L29/66 ,  G11C16/04 ,  G11C11/56

CPC classification number: H01L29/7926 ,  G11C11/5621 ,  G11C16/0483 ,  H01L29/66833 ,  H10B43/27 ,  H10B43/40 ,  G11C2213/71

Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.

公开(公告)号：US09263146B2

公开(公告)日：2016-02-16

申请号：US14208812

申请日：2014-03-13

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： Jin-Ki Kim

IPC: G11C16/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/12

CPC classification number: G11C16/34 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/344 ,  G11C16/3454 ,  G11C2211/5621

Abstract: A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.

公开(公告)号：US09257193B2

公开(公告)日：2016-02-09

申请号：US14156047

申请日：2014-01-15

Applicant: MOSAID TECHNOLOGIES INCORPORATED

Inventor： HakJune Oh ,  Hong Beom Pyeon ,  Jin-Ki Kim

IPC: G11C7/00 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10 ,  G11C16/06

CPC classification number: G11C11/5628 ,  G06F1/12 ,  G11C7/1021 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3445 ,  G11C2207/107

Abstract: An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.

公开(公告)号：US09245640B2

公开(公告)日：2016-01-26

申请号：US14107735

申请日：2013-12-16

Applicant: Mosaid Technologies Incorporated

Inventor： Jin-Ki Kim ,  Peter Gillingham

IPC: G11C16/10 ,  G11C16/30 ,  G11C5/14 ,  G11C16/12 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C5/14 ,  G11C5/143 ,  G11C5/145 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26

Abstract: A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to power the flash memory. Additionally, the memory device includes a second power input to receive a second voltage. The memory device includes power management circuitry configured to receive the second voltage and derive one or more internal voltages. The power management circuitry supplies or conveys the internal voltages to the flash memory. The different internal voltages generated by the power management circuitry (e.g., voltage converter circuit) and supplied to the core memory enable operations such as read/program/erase with respect to cells in the core memory.

公开(公告)号：US08958244B2

公开(公告)日：2015-02-17

申请号：US13836028

申请日：2013-03-15

Applicant: MOSAID Technologies Incorporated

Inventor： Hyoung Seub Rhie

IPC: G11C11/34 ,  G11C16/08 ,  G11C8/08 ,  G11C11/408 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C11/4085 ,  G11C16/0483

Abstract: A non-volatile memory device having a memory array organized into a plurality of memory blocks, having either planar memory cells or stacks of cells. Row decoding circuitry of the memory device is configured to select a group of the plurality of memory blocks in response to a first row address, and to select a memory block of the group for receiving row signals in response to a second row address. Row decoding circuitry associated with each group of memory blocks can have a row pitch spacing that is greater than a row pitch spacing of a single memory block and less than or equal to a total row pitch spacing corresponding to the group of memory blocks.

Abstract translation: 具有组织成多个存储器块的存储器阵列的非易失性存储器件，具有平面存储单元或单元堆叠。 存储器件的行解码电路被配置为响应于第一行地址来选择多个存储器块的组，并且响应于第二行地址选择用于接收行信号的组的存储器块。 与每组存储器块相关联的行解码电路可以具有大于单个存储器块的行间距间隔的行间距间隔，并且小于或等于对应于该组存储器块的总行间距间隔。

公开(公告)号：US08949945B2

公开(公告)日：2015-02-03

申请号：US13724022

申请日：2012-12-21

Applicant: MOSAID Technologies Incorporated

Inventor： James David Larsen

IPC: H04L29/06 ,  H04L12/24

CPC classification number: H04L63/08 ,  H04L41/0213 ,  H04L41/12 ,  H04L63/10 ,  H04L63/20

Abstract: The invention relates to a network and to a method of operating a network. The network comprises a plurality of stations each able to transmit and receive data so that the network can transmit data between stations via at least one selected intermediate station. The network further comprises a plurality of levels of stations including a first level comprising user and/or seed stations, a second level comprising auxiliary stations providing access to auxiliary networks, a third level comprising at least one location management station, and a fourth level comprising at least one authentication station. The method comprises transmitting, from or on behalf of a station on the first level requiring authentication, to an authentication station via one or more stations, an authentication request message. In response, the authentication station transmits authentication data to authenticate the station on the first level.

Abstract translation: 本发明涉及网络和操作网络的方法。 网络包括多个站，每个站能够发送和接收数据，使得网络可以经由至少一个所选择的中间站在站点之间传送数据。 网络还包括多个级别的站，包括包括用户和/或种子站的第一级，第二级包括提供对辅助网络的访问的辅助站，包括至少一个位置管理站的第三级，以及包括 至少一个认证台。 所述方法包括：通过一个或多个站向认证站发送来自或代表要求认证的第一级的站，或者向其发送认证请求消息。 作为响应，认证站发送认证数据以在第一级认证该站。

公开(公告)号：US08923180B2

公开(公告)日：2014-12-30

申请号：US13747802

申请日：2013-01-23

Applicant: MOSAID Technologies Incorporated

Inventor： Nima Ahmadvand ,  Xuejun Lu ,  Hanwu Hu ,  Mouhamadou Lamine Sylla

IPC: H04W52/02 ,  H04W36/00

CPC classification number: H04W52/0206 ,  H04W36/0055 ,  H04W52/02 ,  H04W52/0219 ,  H04W84/12 ,  Y02D70/00 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146 ,  Y02D70/22

Abstract: Power saving in wireless networks is disclosed. A wireless network entity that includes a module to enable a reduction in power consumption in that wireless network entity is also disclosed. The module is configured to determine that a selected wireless station of one or more wireless stations associated with the wireless network entity in a same wireless network will transmit system control information (including synchronization information and service identification information) that is normally transmitted by the wireless network entity.

Abstract translation: 公开了无线网络中的省电。 还公开了一种包括能够降低该无线网络实体中的功率消耗的模块的无线网络实体。 该模块被配置为确定与相同无线网络中的无线网络实体相关联的一个或多个无线站的所选无线站将发送正常由无线网络发送的系统控制信息（包括同步信息和服务标识信息） 实体。