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    CONFIGURATION AND TESTING FOR MAGNETORESISTIVE MEMORY
    142.
    发明申请
    CONFIGURATION AND TESTING FOR MAGNETORESISTIVE MEMORY 有权
    磁记忆体的配置与测试

    公开(公告)号：US20160064058A1

    公开(公告)日：2016-03-03

    申请号：US14837381

    申请日：2015-08-27

    Applicant: Everspin Technologies, Inc.

    Inventor： Jason Janesky ,  Syed M. Alam ,  Dimitri Houssameddine ,  Mark Deherrera

    IPC: G11C11/16 ,  G11C29/12 ,  G11C17/16

    CPC classification number: G11C11/1673 ,  G11C11/16 ,  G11C11/1675 ,  G11C17/16 ,  G11C29/021 ,  G11C29/023 ,  G11C29/026 ,  G11C29/028 ,  G11C29/12 ,  G11C29/50

    Abstract: Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation.

    Abstract translation: 介绍了用于测试和配置磁存储器件的技术和电路。 寄存器和非易失性存储器包含在存储器件中，用于存储用于控制存储器件测试的值以及用于配置与测试和正常操作相关的参数。 示例包括偏置电压的调整，读出放大器偏移值和定时参数，以提高测试操作的效率，以及提高正常操作的可靠性和速度。

    MEMORY DEVICE WITH REDUCED ON-CHIP NOISE
    144.
    发明申请
    MEMORY DEVICE WITH REDUCED ON-CHIP NOISE 审中-公开
    具有减少片上噪声的存储器件

    公开(公告)号：US20150200001A1

    公开(公告)日：2015-07-16

    申请号：US14667888

    申请日：2015-03-25

    Applicant: Everspin Technologies, Inc.

    Inventor： Thomas Andre ,  Syed M. Alam ,  Dietmar Gogl

    IPC: G11C7/02 ,  G11C7/06 ,  G11C5/14

    CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C16/12 ,  G11C16/30

    Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

    Abstract translation: 在一些示例中，存储器件包括配备有隔离开关和专用电源引脚的多个存储体。 每个存储体的隔离开关被配置为将存储体与全局信号隔离。 专用电源引脚被配置为将每个存储器组连接到封装衬底上的专用本地电源焊盘，以向每个存储体提供本地专用电源，并且通过设备上的导体来减少存储体之间的电压传输 ，器件衬底或存储器件的封装衬底。

    Circuit and method for spin-torque MRAM bit line and source line voltage regulation
    145.
    发明授权
    Circuit and method for spin-torque MRAM bit line and source line voltage regulation 有权
    自旋扭矩MRAM位线和源极线电压调节的电路和方法

    公开(公告)号：US09047965B2

    公开(公告)日：2015-06-02

    申请号：US13720183

    申请日：2012-12-19

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1693

    Abstract: Circuitry and a method for regulating voltages applied to source and bit lines of a spin-torque magnetoresistive random access memory (ST-MRAM) reduces time-dependent dielectric breakdown stress of the word line transistors. During a read or write operation, only the selected bit lines and source lines are pulled down to a low voltage and/or pulled up to a high voltage depending on the operation (write 0, write 1, and read) being performed. The unselected bit lines and source lines are held at the voltage while separately timed signals pull up or pull down the selected bit lines and source lines during read and write operations.

    Abstract translation: 用于调节施加到自旋扭矩磁阻随机存取存储器（ST-MRAM）的源极和位线的电压的电路和方法降低了字线晶体管的时间依赖介电击穿应力。 在读或写操作期间，根据所执行的操作（写0，写1和读），只将所选择的位线和源极线拉低至低电压和/或上拉至高电压。 未选择的位线和源极线保持在电压，而在读取和写入操作期间单独定时的信号上拉或下拉所选位线和源极线。

    Memory device with reduced on-chip noise
    146.
    发明授权
    Memory device with reduced on-chip noise 有权
    具有降低片内噪声的存储器件

    公开(公告)号：US09019794B2

    公开(公告)日：2015-04-28

    申请号：US14050625

    申请日：2013-10-10

    Applicant: Everspin Technologies, Inc.

    Inventor： Thomas Andre ,  Syed M. Alam ,  Dietmar Gogl

    IPC: G11C8/12 ,  G11C7/02 ,  G11C5/14 ,  G11C16/12 ,  G11C16/30

    CPC classification number: G11C7/02 ,  G11C5/14 ,  G11C5/145 ,  G11C5/146 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/12 ,  G11C16/12 ,  G11C16/30

    Abstract: In some examples, a memory device includes multiple memory banks equipped with an isolation switch and dedicated power supply pins. The isolation switch of each memory bank is configured to isolate the memory bank from global signals. The dedicated power supply pins are configured to connect each of the memory banks to a dedicated local power supply pads on the package substrate to provide local dedicated power supplies to each of the memory banks and to reduce voltage transfer between memory banks over conductors on the device, the device substrate, or the package substrate of the memory device.

    Abstract translation: 在一些示例中，存储器件包括配备有隔离开关和专用电源引脚的多个存储体。 每个存储体的隔离开关被配置为将存储体与全局信号隔离。 专用电源引脚被配置为将每个存储器组连接到封装衬底上的专用本地电源焊盘，以向每个存储体提供本地专用电源，并且通过器件上的导体来减少存储体之间的电压传输 ，器件衬底或存储器件的封装衬底。

    METHOD FOR HEALING RESET ERRORS IN A MAGNETIC MEMORY
    148.
    发明申请
    METHOD FOR HEALING RESET ERRORS IN A MAGNETIC MEMORY 审中-公开
    治疗磁记录中复位错误的方法

    公开(公告)号：US20140372792A1

    公开(公告)日：2014-12-18

    申请号：US14297386

    申请日：2014-06-05

    Applicant: Everspin Technologies, Inc.

    Inventor： Jon Slaughter ,  Dimitri Houssameddine ,  Thomas Andre ,  Syed M. Alam

    IPC: G06F11/07

    CPC classification number: G06F11/073 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677

    Abstract: A method is provided for healing reset errors for a magnetic memory using destructive read with selective write-back, including for example, a self-referenced read of spin-torque bits in an MRAM. Memory cells are prepared for write back by one of identifying memory cells determined in error using an error correcting code and inverting the inversion bit for those memory cells determined in error; identifying memory cells determined in error using an error correcting code and resetting a portion of the memory cells to the first state; and resetting one or more memory cells to the first state.

    Abstract translation: 提供了一种用于使用具有选择性回写的破坏性读取来恢复磁存储器的复位错误的方法，包括例如MRAM中的自旋转矩位的自参考读取。 存储单元被准备用于使用错误校正码错误地确定的识别存储器单元中的一个进行写回，并且将错误地确定的那些存储器单元的反转位反相; 使用纠错码识别误差确定的存储器单元，并将所述存储器单元的一部分重置为所述第一状态; 以及将一个或多个存储器单元重置为第一状态。

    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE
    149.
    发明申请
    TAMPER DETECTION AND RESPONSE IN A MEMORY DEVICE 有权
    在记忆体设备中的篡改检测和响应

    公开(公告)号：US20140226396A1

    公开(公告)日：2014-08-14

    申请号：US14175337

    申请日：2014-02-07

    Applicant: EVERSPIN TECHNOLOGIES, INC.

    Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

    IPC: G11C7/24 ,  G11C11/16

    CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation.

    Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，存储器设备上的响应包括禁用一个或多个存储器操作并产生模拟电流以仿真在正常操作期间预期的电流。

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