公开(公告)号：US20160343621A1

公开(公告)日：2016-11-24

申请号：US15229754

申请日：2016-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li ,  Junli Wang

IPC: H01L21/8238 ,  H01L27/12 ,  H01L29/06 ,  H01L21/02 ,  H01L29/161 ,  H01L29/16 ,  H01L29/20 ,  H01L21/84 ,  H01L27/092 ,  H01L29/10

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure. A silicon germanium alloy fin is formed on opposing sidewalls of each semiconductor mandrel structure that is present in a pFET device region of the semiconductor substrate and directly on a surface of each first oxide isolation structure. Each semiconductor mandrel structure is removed and a second oxide isolation structure is formed between each first oxide isolation structure and extending beneath a bottommost surface of each first oxide isolation structure.

Abstract translation: 形成从半导体衬底的剩余部分向上延伸的半导体芯棒结构。 第一氧化物隔离结构形成在半导体衬底的剩余部分的暴露表面和每个半导体芯棒结构之间。 在每个半导体芯棒结构的相对的侧壁上形成硅锗合金翅片，其存在于半导体衬底的pFET器件区域中并且直接位于每个第一氧化物隔离结构的表面上。 去除每个半导体芯棒结构，并且在每个第一氧化物隔离结构之间形成第二氧化物隔离结构，并延伸到每个第一氧化物隔离结构的最下表面之下。

公开(公告)号：US09484440B2

公开(公告)日：2016-11-01

申请号：US14752095

申请日：2015-06-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  Renesas Electronics Corporation

Inventor： Hong He ,  Shogo Mochizuki ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L27/088 ,  H01L29/06 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L27/0886 ,  H01L21/02271 ,  H01L21/0257 ,  H01L21/30604 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7851

Abstract: Semiconductor devices having non-merged fin extensions and methods for forming the same. Methods for forming semiconductor devices include forming fins on a substrate; forming a dummy gate over the fins, leaving a source and drain region exposed; etching the fins below a surface level of a surrounding insulator layer; and epitaxially growing fin extensions from the etched fins.

Abstract translation: 具有非合并翅片延伸的半导体器件及其形成方法。 用于形成半导体器件的方法包括在衬底上形成翅片; 在翅片上形成虚拟栅极，留下源极和漏极区域; 在低于周围绝缘体层的表面水平面处蚀刻散热片; 并从蚀刻的翅片外延生长翅片延伸部分。

公开(公告)号：US20160300721A1

公开(公告)日：2016-10-13

申请号：US15182995

申请日：2016-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/31122 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US09431425B1

公开(公告)日：2016-08-30

申请号：US14674586

申请日：2015-03-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Juntao Li ,  Junli Wang

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/12 ,  H01L21/84 ,  H01L27/092 ,  H01L29/161 ,  H01L29/06 ,  H01L21/762 ,  H01L29/16 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/76229 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/161 ,  H01L29/20

Abstract: Semiconductor mandrel structures are formed extending upward from a remaining portion of a semiconductor substrate. A first oxide isolation structure is formed on exposed surfaces of the remaining portion of the semiconductor substrate and between each semiconductor mandrel structure. A silicon germanium alloy fin is formed on opposing sidewalls of each semiconductor mandrel structure that is present in a pFET device region of the semiconductor substrate and directly on a surface of each first oxide isolation structure. Each semiconductor mandrel structure is removed and a second oxide isolation structure is formed between each first oxide isolation structure and extending beneath a bottommost surface of each first oxide isolation structure.

Abstract translation: 形成从半导体衬底的剩余部分向上延伸的半导体芯棒结构。 第一氧化物隔离结构形成在半导体衬底的剩余部分的暴露表面和每个半导体芯棒结构之间。 在每个半导体芯棒结构的相对的侧壁上形成硅锗合金翅片，其存在于半导体衬底的pFET器件区域中并且直接位于每个第一氧化物隔离结构的表面上。 去除每个半导体芯棒结构，并且在每个第一氧化物隔离结构之间形成第二氧化物隔离结构，并延伸到每个第一氧化物隔离结构的最下表面之下。

公开(公告)号：US09391155B2

公开(公告)日：2016-07-12

申请号：US14953908

申请日：2015-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

公开(公告)号：US20160190288A1

公开(公告)日：2016-06-30

申请号：US14743504

申请日：2015-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions.

Abstract translation: 实施例涉及一种对FinFET的鳍进行富集和电绝缘的方法。 该方法包括形成至少一个翅片。 所述方法还包括在第一组条件下形成所述至少一个翅片的富集的上部部分。 所述方法还包括在第二组条件下形成与所述至少一个翅片的下部分的电隔离区域，其中在所述第一组条件下的形成与所述第二组条件下的成形间隔开。 该方法还包括与第二组条件分开地控制第一组条件。

公开(公告)号：US09379218B2

公开(公告)日：2016-06-28

申请号：US14584790

申请日：2014-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

Abstract translation: 一种形成半导体器件的方法，包括在包括鳍结构的硅上形成包括鳍结构的硅并形成含锗层。 然后，锗从含锗层扩散到包括鳍结构的硅中，以将包括鳍结构的硅转化为包括鳍结构的硅锗。

公开(公告)号：US09368350B1

公开(公告)日：2016-06-14

申请号：US14747487

申请日：2015-06-23

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chi-Chun Liu ,  Alexander Reznicek ,  Chiahsun Tseng ,  Tenko Yamashita

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L29/0657

Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.

Abstract translation: 一种用于DSA鳍图形化的方法包括在光刻叠层上形成BCP层，所述BCP层具有第一和第二块，所述光刻堆叠设置在硬掩模和衬底上，并且所述硬掩模包括第一和第二电介质层; 移除所述第一块以在所述BCP层中与所述第二块定义鳍图案; 将鳍状图案蚀刻到第一介电层中; 用色调反转材料填充翅片图案; 蚀刻过度填充鳍图案的色调反转材料; 从所述色调反转材料中选择性地去除所述第一介质层以限定反转的翅片图案; 将倒置的翅片图案蚀刻到硬掩模的第二介电层中; 去除色调反转材料; 并将第二介电层的倒置鳍状图案转印到基板中以限定翅片。

公开(公告)号：US09331148B1

公开(公告)日：2016-05-03

申请号：US14962194

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成翅片，在鳍片和衬底上形成虚拟栅极堆叠，去除鳍片的暴露部分的一部分，在曝光的部分上形成源极/漏极区域 在所述源极/漏极区域上形成导电接触，去除所述伪栅极堆叠以暴露所述鳍片的沟道区域，在所述鳍片的沟道区域中注入离子，执行退火处理，以及形成栅极叠层 在翅片的通道区域上。

公开(公告)号：US20160027806A1

公开(公告)日：2016-01-28

申请号：US14874388

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek ,  Soon-Cheon Seo

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L27/1211 ,  H01L21/823412 ,  H01L29/04 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.