公开(公告)号：US08120176B2

公开(公告)日：2012-02-21

申请号：US12722794

申请日：2010-03-12

Applicant: Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

Inventor： Dong-Kil Shin ,  Shle-Ge Lee ,  Jong-Joo Lee ,  Jong-Ho Lee

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1132 ,  H01L2224/1134 ,  H01L2224/11464 ,  H01L2224/13006 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate and a bonding pad disposed thereon. The semiconductor device also includes a passivation layer, a buffer layer, and an insulating layer sequentially stacked on the semiconductor substrate. According to one aspect, a first recess is defined within the passivation layer, the buffer layer, and the insulating layer to expose at least a region of the bonding pad and a second recess is defined within the insulating layer to expose at least a region of the buffer layer and spaced apart from the first recess such that a portion of the insulating layer is interposed therebetween. Further, the semiconductor device includes a conductive solder bump disposed within the first and second recesses. The conductive solder bump may be connected to the bonding pad in the first recess and supported by the buffer layer through a protrusion of the conductive solder bump extending into the second recess.

Abstract translation: 在一个实施例中，半导体器件包括半导体衬底和设置在其上的接合焊盘。 半导体器件还包括依次堆叠在半导体衬底上的钝化层，缓冲层和绝缘层。 根据一个方面，在钝化层，缓冲层和绝缘层内限定第一凹槽，以露出焊盘的至少一个区域，并且在绝缘层内限定第二凹槽，以暴露至少一个区域 缓冲层，并且与第一凹部间隔开，使得绝缘层的一部分插入其间。 此外，半导体器件包括设置在第一和第二凹槽内的导电焊料凸块。 导电焊料凸块可以连接到第一凹槽中的焊盘，并且通过延伸到第二凹部中的导电焊料凸块的突起被缓冲层支撑。

公开(公告)号：US08110990B2

公开(公告)日：2012-02-07

申请号：US12314358

申请日：2008-12-09

Applicant: Bum Ho Choi ,  Jong Ho Lee ,  Jung Chan Bae ,  Yong-Seok Park ,  Chun-Seong Park ,  Woo Sam Kim ,  Gil Sik Lee ,  Lawrence John Overzet ,  Byeong Jun Lee

Inventor： Bum Ho Choi ,  Jong Ho Lee ,  Jung Chan Bae ,  Yong-Seok Park ,  Chun-Seong Park ,  Woo Sam Kim ,  Gil Sik Lee ,  Lawrence John Overzet ,  Byeong Jun Lee

IPC: H05B31/26

CPC classification number: H01J37/32541 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32825

Abstract: Disclosed is an atmospheric pressure plasma apparatus for enhancing and or controlling the dissociation of a secondary gas by converting a source gas into a plasma state at atmospheric pressure and controlling the interaction between that plasma and the secondary gas using porous metal, and ceramic tubes to create a path having controllable isolation from the region where plasma is generated.

Abstract translation: 公开了一种大气压等离子体装置，用于通过将源气体转化为大气压下的等离子体状态来增强和/或控制二次气体的解离，并使用多孔金属控制该等离子体和二次气体之间的相互作用，以及陶瓷管以产生 与产生等离子体的区域具有可控隔离的路径。

公开(公告)号：US20110317950A1

公开(公告)日：2011-12-29

申请号：US13067815

申请日：2011-06-28

Applicant: Jong Ho Lee

Inventor： Jong Ho Lee

IPC: F16C32/06

CPC classification number: F16C33/745 ,  F16C17/105 ,  F16C33/107 ,  F16C2370/12

Abstract: Disclosed is a motor device. The motor device according to an exemplary embodiment of the present invention includes a sleeve having a shaft hole expanding downwardly in an axial direction; a shaft having a head part having exposed to a top portion of the sleeve and a body part having a shape corresponding to the shaft hole; a rotor case combined to the head part and rotating in connection with the shaft; an oil sealing part formed between the rotor case and the sleeve and an oil interface to seal oil provided to have a taper shape; and a thrust dynamic part formed on at least one of the rotor case and the sleeve and pumping the oil interface in an inner-diameter direction from the oil interface at the time of the rotation of the rotor case.

Abstract translation: 公开了一种电动机装置。 根据本发明的示例性实施例的电动机装置包括具有沿轴向向下膨胀的轴孔的套筒; 具有暴露于所述套筒的顶部的头部的轴和具有与所述轴孔对应的形状的主体部; 转子壳体组合到头部并且与轴连接旋转; 形成在所述转子壳体和所述套筒之间的油封部，以及用于密封设置成具有锥形形状的油的油接口; 以及形成在所述转子壳体和所述套筒中的至少一个上的推力动力部件，并且在所述转子壳体旋转时从所述油界面沿内径方向抽吸所述油界面。

公开(公告)号：US08054319B2

公开(公告)日：2011-11-08

申请号：US12487198

申请日：2009-06-18

Applicant: Kwang-Kee Lee ,  Jong-Ho Lee ,  Sung-Wook Byun ,  Un-Gyo Jung ,  Glenn A. Adams

Inventor： Kwang-Kee Lee ,  Jong-Ho Lee ,  Sung-Wook Byun ,  Un-Gyo Jung ,  Glenn A. Adams

IPC: G09G5/00 ,  H04N9/74 ,  H04N5/445 ,  G06F3/00 ,  G06F13/00

CPC classification number: H04N5/45 ,  H04N21/4316 ,  H04N21/43615 ,  H04N21/4433 ,  H04N21/4622

Abstract: The present invention performs multiscreen configuration and multiscreen management by using a plurality of screens and a plurality of methods in order to represent a plurality of service contents. In accordance with a multiscreen configuration method of the present invention, by mutually assigning one or more broadcasting services, one or more logical screens, one or more display screens, and one or more output ports, ultimately outputting service contents which are executed on screens assigned by output ports, and setting, changing, and reporting configuration of a multiscreen, the configuration of the multiscreen may be set or reset so as to effectively output various service contents on the multiscreen by using a desired method.

Abstract translation: 本发明通过使用多个屏幕和多种方法来执行多屏幕配置和多屏幕管理，以便表示多个服务内容。 根据本发明的多屏配置方法，通过相互分配一个或多个广播服务，一个或多个逻辑屏幕，一个或多个显示屏幕和一个或多个输出端口，最终输出在分配的屏幕上执行的服务内容 通过输出端口以及多屏幕的设置，改变和报告配置，可以设置或重置多画面的配置，以便通过使用期望的方法在多画面上有效地输出各种服务内容。

公开(公告)号：US20110254076A1

公开(公告)日：2011-10-20

申请号：US13055881

申请日：2008-05-08

Applicant: Jong-Ho Lee

Inventor： Jong-Ho Lee

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0483 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/8616

Abstract: Provided is an ultra highly-integrated flash memory cell device. The cell device includes a semiconductor substrate, a first doping semiconductor area formed on the semiconductor substrate, a second doping semiconductor area formed on the first doping semiconductor area, and a tunneling insulating layer, a charge storage node, a control insulating layer, and a control electrode which are sequentially formed on the second doping semiconductor area. The first and second doping semiconductor areas are doped with impurities of the different semiconductor types According to the present invention, it is possible to greatly improve miniaturization characteristics and performance of the cell devices in conventional NOR or NAND flash memories. Unlike conventional transistor type cell devices, the cell device according to the present invention does not have a channel and a source/drain. Therefore, in comparison with the conventional memories, the fabricating process can be simplified, and the problem such as cross-talk or read disturb can be greatly reduced.

Abstract translation: 提供了一种超高度集成的闪存单元设备。 电池器件包括半导体衬底，形成在半导体衬底上的第一掺杂半导体区域，形成在第一掺杂半导体区域上的第二掺杂半导体区域，以及隧穿绝缘层，电荷存储节点，控制绝缘层和 控制电极依次形成在第二掺杂半导体区域上。 第一掺杂半导体区域和第二掺杂半导体区域掺杂有不同半导体类型的杂质根据本发明，可以大大提高常规NOR或NAND闪存中的单元装置的小型化特性和性能。 与传统晶体管型电池器件不同，根据本发明的电池器件不具有沟道和源极/漏极。 因此，与常规存储器相比，可以简化制造过程，并且可以大大减少串扰或读取干扰等问题。

公开(公告)号：US20110244634A1

公开(公告)日：2011-10-06

申请号：US13103553

申请日：2011-05-09

Applicant: Young-Lyong Kim ,  Jong-Ho Lee ,  Cheul-Joong Youn ,  Eun-Chul Ahn

Inventor： Young-Lyong Kim ,  Jong-Ho Lee ,  Cheul-Joong Youn ,  Eun-Chul Ahn

IPC: H01L21/56

CPC classification number: H01L25/105 ,  H01L24/73 ,  H01L24/91 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package includes a first package that a first semiconductor chip is mounted on a front side of a first substrate and a redistributed pad including a first redistributed pad electrically connected to the first substrate and a second redistributed pad electrically connected to the first redistributed pad is disposed on the first semiconductor chip and a second package that a second semiconductor chip is mounted on a front side of a second substrate, the second package including a connection member electrically connected to the second redistributed pad. The connection member electrically connected to the redistributed pad electrically connects the first and second packages to each other.

Abstract translation: 半导体封装以及半导体封装的制造方法。 半导体封装包括第一封装，第一半导体芯片安装在第一基板的前侧，以及重新分布的焊盘，其包括电连接到第一基板的第一再分布焊盘和电连接到第一再分布焊盘的第二再分布焊盘 设置在第一半导体芯片上的第二封装以及第二半导体芯片安装在第二基板的正面上的第二封装，所述第二封装包括与第二再分布焊盘电连接的连接部件。 电连接到再分布垫的连接构件将第一和第二封装彼此电连接。

公开(公告)号：US08013937B2

公开(公告)日：2011-09-06

申请号：US11496482

申请日：2006-08-01

Applicant: Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn A. Adams

Inventor： Jong-ho Lee ,  Kwang-kee Lee ,  Un-gyo Jung ,  Glenn A. Adams

IPC: H04N5/45

CPC classification number: G09G5/14 ,  G09G2340/0407 ,  G09G2340/0464 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/125 ,  H04N5/445 ,  H04N5/44591 ,  H04N5/45 ,  H04N21/4312 ,  H04N21/4314 ,  H04N21/4316 ,  H04N21/443 ,  H04N21/4622

Abstract: An apparatus for providing multiple screens and a method of dynamically configuring multiple screens are provided. The apparatus for providing multiple screens includes a digital signal processing module which receives video information, audio information, or data information and restores a service based on the video information, the audio information or the data information, a service processing module which generates a plurality of logical screens and an overlay screen for displaying the restored service, and an output module which maps the plurality of logical screens generated by the service processing module to different locations on a display screen and allows the overlay screen to overlay the display screen.

Abstract translation: 提供了一种用于提供多个屏幕的装置和一种动态配置多个屏幕的方法。 用于提供多个屏幕的装置包括：数字信号处理模块，其接收视频信息，音频信息或数据信息，并且基于视频信息，音频信息或数据信息恢复服务;服务处理模块，其生成多个 用于显示恢复的服务的逻辑屏幕和覆盖屏幕;以及输出模块，其将由服务处理模块生成的多个逻辑屏幕映射到显示屏幕上的不同位置，并允许覆盖屏幕覆盖显示屏幕。

公开(公告)号：US08013402B2

公开(公告)日：2011-09-06

申请号：US12574912

申请日：2009-10-07

Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

IPC: H01L21/02

CPC classification number: H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

公开(公告)号：US20110210311A1

公开(公告)日：2011-09-01

申请号：US13035063

申请日：2011-02-25

Applicant: Je Won KIM ,  Tae Sung Jang ,  Jong Gun Woo ,  Jong HO Lee

Inventor： Je Won KIM ,  Tae Sung Jang ,  Jong Gun Woo ,  Jong HO Lee

IPC: H01L33/06

CPC classification number: H01L33/08 ,  H01L27/156 ,  H01L33/50 ,  H01L33/62 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor light emitting device includes: a substrate; a plurality of light emitting cells arranged on the substrate, each of the light emitting cells including a first-conductivity-type semiconductor layer, a second-conductivity-type semiconductor layer, and an active layer disposed therebetween to emit blue light; an interconnection structure electrically connecting at least one of the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer of the light emitting cell to at least one of the first-conductivity-type semiconductor layer and the second-conductivity-type semiconductor layer of another light emitting cell; and a light conversion part formed in at least a portion of a light emitting region defined by the plurality of light emitting cells, the light conversion part including at least one of a red light conversion part having a red light conversion material and a green light conversion part having a green light conversion material.

公开(公告)号：US08008771B2

公开(公告)日：2011-08-30

申请号：US12193561

申请日：2008-08-18

Applicant: Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

Inventor： Pyoung-Wan Kim ,  Eun-Chul Ahn ,  Jong-Ho Lee ,  Teak-Hoon Lee ,  Chul-Yong Jang

IPC: H01L23/48

CPC classification number: H01L23/49816 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/5389 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/12105 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor chip package including a semiconductor chip including a first surface having bonding pads, a second surface facing the first surface, and sidewalls; a molding extension part surrounding the second surface and the sidewalls of the semiconductor chip; redistribution patterns extending from the bonding pads over the molding extension part, and electrically connected to the bonding pads; bump solder balls on the redistribution patterns; and a molding layer configured to cover the first surface of the semiconductor chip and the molding extension part, while exposing portions of each of the bump solder balls. The molding layer has concave meniscus surfaces between the bump solder balls adjacent to each other.

Abstract translation: 一种半导体芯片封装，包括：半导体芯片，包括具有接合焊盘的第一表面，与所述第一表面相对的第二表面和侧壁; 围绕半导体芯片的第二表面和侧壁的成型延伸部分; 重新分布图案从接合焊盘延伸到模制延伸部分上，并且电连接到焊盘; 碰撞焊球上的再分布图案; 以及模制层，其被配置为覆盖半导体芯片的第一表面和模制延伸部分，同时暴露每个凸块焊球的部分。 成型层在彼此相邻的凸块焊料球之间具有凹面弯月面。