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180 条记录 (耗时 0.028 秒)

    Mixed memory integration with NVRAM, dram and sram cell structures on same substrate
    151.
    发明授权
    Mixed memory integration with NVRAM, dram and sram cell structures on same substrate 有权
    与同一基板上的NVRAM，串联和sram单元结构的混合存储器集成

    公开(公告)号：US06424011B1

    公开(公告)日：2002-07-23

    申请号：US09387059

    申请日：1999-08-31

    申请人： Fariborz Assaderaghi ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman

    发明人： Fariborz Assaderaghi ,  Louis Lu-Chen Hsu ,  Jack A. Mandelman

    IPC分类号： H01L2701

    CPC分类号： H01L27/10894 ,  G11C11/005 ,  H01L27/105 ,  H01L27/10808 ,  H01L27/10852 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11526

    摘要： A semiconductor memory device including an NVRAM cell structure, a DRAM cell structure and an SRAM cell structure. The NVRAM cell structure, the DRAM cell structure, and the SRAM cell structure are on the same semiconductor on insulator substrate. An NVRAM cell structure. Processes for forming a memory structure that includes NVRAM, DRAM, and/or SRAM memory structures on one semiconductor on insulator substrate and processes for forming a new NVRAM cell structure. Preferably, the semiconductor-on-insulator substrate is an SOI substrate, a silicon on glass substrate or a silicon on sapphire substrate, as appropriate for a particular application.

    摘要翻译： 一种包括NVRAM单元结构，DRAM单元结构和SRAM单元结构的半导体存储器件。 NVRAM单元结构，DRAM单元结构和SRAM单元结构在同一半导体衬底上。 NVRAM单元结构。 用于形成在一个半导体绝缘体衬底上的NVRAM，DRAM和/或SRAM存储器结构的存储器结构的工艺和用于形成新的NVRAM单元结构的工艺。 优选地，绝缘体上半导体衬底是适合于特定应用的SOI衬底，玻璃衬底上的硅或蓝宝石衬底上的硅。

    Ramp-up rate control circuit for flash memory charge pump
    152.
    发明授权
    Ramp-up rate control circuit for flash memory charge pump 失效
    闪存充电泵的升压速率控制电路

    公开(公告)号：US5872733A

    公开(公告)日：1999-02-16

    申请号：US730628

    申请日：1996-10-21

    申请人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary Joseph Saccamango ,  Hyun Jong Shin

    发明人： Taqi Nasser Buti ,  Louis Lu-Chen Hsu ,  Jente B. Kuang ,  Somnuk Ratanaphanyarat ,  Mary Joseph Saccamango ,  Hyun Jong Shin

    IPC分类号： G11C16/30 ,  H03K5/04 ,  H03F3/16 ,  H03L7/00

    CPC分类号： G11C16/30 ,  H03K5/04

    摘要： An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.

    摘要翻译： 一种用于控制具有提供输出电压和输出电流的输出的电荷泵的上升速率的装置。 在一个实施例中，该装置包括具有输入，适于连接到地电势的输出和至少一个具有栅极，源极，漏极和主体的晶体管的电流泄放电路，并且限定源极和漏极之间的至少一个电流路径 形成输入和输出之间的当前路径。 主体适用于连接到电荷泵输出。 该装置还包括具有适于连接到电荷泵输出的输入端的控制电路和连接到泄放电路输入端的输出端。 控制电路为电流放电电路的输入提供电压电位，以控制电流放电电路晶体管的栅极 - 源极电压。 通过电流泄放路径的电流路径的电流流动是电荷泵输出的大小和泄放电路晶体管的栅极 - 源极电压的函数。 本文描述了本发明装置的其它实施例。

    High performance on-chip voltage regulator designs
    154.
    发明授权
    High performance on-chip voltage regulator designs 失效
    高性能片上稳压器设计

    公开(公告)号：US5721485A

    公开(公告)日：1998-02-24

    申请号：US582815

    申请日：1996-01-04

    申请人： Louis Lu-Chen Hsu ,  Toshiaki Kirihata ,  Somnuk Ratanaphanyarat ,  Hyun Jong Shin

    发明人： Louis Lu-Chen Hsu ,  Toshiaki Kirihata ,  Somnuk Ratanaphanyarat ,  Hyun Jong Shin

    IPC分类号： G06F1/26 ,  H03K3/01

    CPC分类号： G06F1/26 ,  Y10S323/901

    摘要： High performance on-chip voltage regulator designs are disclosed which have settling times which are fast enough to meet today's microprocessor/microcontroller requirements when they are entering an active mode from a passive mode. A first preferred embodiment provides a circuit in which a single pulse control signal is required to instantly raise Vy when the microprocessor is in the wake-up period. The circuit includes a charge pump, a differential amplifier, and a microprocessor connected to the power supply through a voltage regulating device. A second embodiment provides a circuit to stimulate Vint prior to CPU wake-up. The principle of operation of this embodiment is to stimulate the voltage regulating device prior to CPU wake-up. By stimulating (pulling down) the Vint node, the voltage regulating device will raise Vy and ready the microprocessor to draw a large current.

    摘要翻译： 公开了高性能片上稳压器设计，其具有足够快的建立时间，以在从被动模式进入活动模式时满足当今的微处理器/微控制器要求。 第一优选实施例提供了一种电路，其中当微处理器处于唤醒期间时，需要单脉冲控制信号来立即升高Vy。 电路包括电荷泵，差分放大器和通过电压调节装置连接到电源的微处理器。 第二实施例提供了在CPU唤醒之前刺激Vint的电路。 该实施例的操作原理是在CPU唤醒之前刺激电压调节装置。 通过刺激（下拉）Vint节点，电压调节装置将升高Vy并准备好微处理器绘制大电流。

    Packing density for flash memories
    155.
    发明授权
    Packing density for flash memories 失效
    闪存的包装密度

    公开(公告)号：US5622881A

    公开(公告)日：1997-04-22

    申请号：US319393

    申请日：1994-10-06

    申请人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    发明人： Joyce E. Acocella ,  Carol Galli ,  Louis Lu-Chen Hsu ,  Seiki Ogura ,  Nivo Rovedo ,  Joseph F. Shepard

    IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

    CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546 ,  Y10S148/117 ,  Y10S438/981

    摘要： Improved packing density as well as improved performance and manufacturing yield is achieved in an electrically programmable memory by confining floating gate structures between isolation structures covered with a thin nitride layer. The confinement of the floating gate is achieved by planarization, preferably with a self-limiting chemical/mechanical polishing process, to the surface of the nitride layer covering the isolation structures. Gate oxide and control electrode connections can then be formed on a substantially planar surface without compromising the quality of the gate oxide or breakdown voltage the device must withstand for programming. Since severe topology is avoided over which these connections are formed, improved formation of low resistance connections, possibly including metal connections, are possible and allow scaling of transistors of the memory cells to be scaled to sizes not previously possible.

    摘要翻译： 通过将浮置栅极结构限制在被薄氮化物层覆盖的隔离结构之间，可在电可编程存储器中实现提高的封装密度以及改进的性能和制造产量。 浮栅的限制是通过平面化，优选采用自限制化学/机械抛光工艺，覆盖覆盖隔离结构的氮化物层的表面来实现的。 然后可以在基本平坦的表面上形成栅极氧化物和控制电极连接，而不会损害器件必须承受编程的栅极氧化物的质量或击穿电压。 由于避免了形成这些连接的严格的拓扑结构，所以可能包括可能包括金属连接的低电阻连接的形成得到改进，并且允许将存储器单元的晶体管缩放到先前不可能的尺寸。