公开(公告)号：US12111545B2

公开(公告)日：2024-10-08

申请号：US18233953

申请日：2023-08-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Koji Kusunoki ,  Susumu Kawashima ,  Daisuke Kubota ,  Tetsuji Ishitani ,  Akio Yamashita

IPC: G02F1/1362 ,  C09K19/38 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/137

CPC classification number: G02F1/13624 ,  C09K19/3857 ,  G02F1/133345 ,  G02F1/133357 ,  G02F1/133365 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/1368 ,  G02F1/13756

Abstract: A display device with a high aperture ratio is provided. The display device includes, in a pixel, a first transistor, a second transistor, a first insulating layer, a second insulating layer, a conductive layer, a pixel electrode, a layer containing a liquid crystal material, and a common electrode. The first insulating layer is positioned over a channel formation region of the first transistor. The conductive layer is positioned over the first insulating layer. The second insulating layer is positioned over the first transistor, the second transistor, the first insulating layer, and the conductive layer. The pixel electrode is positioned over the second insulating layer, the layer containing a liquid crystal material is positioned over the pixel electrode, and the common electrode is positioned over the layer containing a liquid crystal material. The common electrode overlaps with the conductive layer with the layer containing a liquid crystal material and the pixel electrode therebetween. The pixel includes a first connection portion where the conductive layer is electrically connected to the first transistor and a second connection portion where the pixel electrode is electrically connected to the second transistor. The conductive layer, the pixel electrode, and the common electrode each have a function of transmitting visible light.

公开(公告)号：US20240332262A1

公开(公告)日：2024-10-03

申请号：US18740603

申请日：2024-06-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Yuki OKAMOTO ,  Shunpei YAMAZAKI

IPC: H01L25/065 ,  G11C5/06 ,  H01L23/00 ,  H01L29/786 ,  H10B12/00

CPC classification number: H01L25/0657 ,  G11C5/063 ,  H01L29/78693 ,  H10B12/315 ,  H10B12/50 ,  H01L24/16 ,  H01L25/0655 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

公开(公告)号：US20240331641A1

公开(公告)日：2024-10-03

申请号：US18293869

申请日：2022-07-28

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI

IPC: G09G3/3266 ,  G06F3/042 ,  G06V40/13 ,  G09G3/3233

CPC classification number: G09G3/3266 ,  G06F3/042 ,  G06V40/1318 ,  G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0842 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2354/00 ,  G09G2360/14

Abstract: To provide a display apparatus with a novel structure. A display portion including a first subpixel, a second subpixel, a first gate line supplied with a first selection signal to scan the first subpixel, and a second gate line supplied with a second selection signal to scan the second subpixel; and a driver control circuit including a gate line driver circuit, a switching portion that allots the first selection signal or the second selection signal output from the gate line driver circuit to the first gate line or the second gate line to be output, and a timing control circuit that controls the switching portion are included. The timing control circuit allows the gate line driver circuit to output the first selection signal of a first frame frequency and the second selection signal having a selection period longer than the first selection signal in a first operation mode, and to output the first selection signal and the second selection signal with a second frame frequency lower than the first frame frequency in a second operation mode.

公开(公告)号：US12106823B2

公开(公告)日：2024-10-01

申请号：US17914845

申请日：2021-04-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeya Hirose ,  Seiichi Yoneda ,  Takayuki Ikeda ,  Shunpei Yamazaki

IPC: G11C7/16 ,  G11C11/40 ,  G11C27/02 ,  H01L29/786 ,  G11C11/54

CPC classification number: G11C7/16 ,  G11C11/40 ,  G11C27/02 ,  H01L29/786 ,  G11C11/54

Abstract: A semiconductor device capable of holding analog data is provided. Two holding circuits, two bootstrap circuits, and one source follower circuit are formed with use of four transistors and two capacitors. A memory node is provided in each of the two holding circuits; a data potential is written to one of the memory nodes and a reference potential is written to the other of the memory nodes. At the time of data reading, the potential of the one memory node is increased in one of the bootstrap circuits, and the potential of the other memory node is increased in the other of the bootstrap circuits. A potential difference between the two memory nodes is output by the source follower circuit. With use of the source follower circuit, the output impedance can be reduced.

公开(公告)号：US12103481B2

公开(公告)日：2024-10-01

申请号：US18381330

申请日：2023-10-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Takayuki Ikeda ,  Yoshiyuki Kurokawa

IPC: B60R21/00 ,  B60R21/0134 ,  G06V20/56 ,  B60R21/01 ,  B60R21/013

CPC classification number: B60R21/0134 ,  B60R21/00 ,  G06V20/56 ,  B60R2021/01013 ,  B60R2021/01211 ,  B60R21/013 ,  G06T2207/30252

Abstract: An occupant protection device which can protect an occupant without delay is provided. An image taken by an imaging device is analyzed to judge whether there is an object approaching the subject car. In the case where a collision between the object and the subject car is judged to be inevitable, an airbag device is activated before the collision, whereby the occupant can be protected without delay. By using selenium for a light-receiving element of the imaging device, an accurate image can be obtained even under low illuminance. Imaging in a global shutter system leads to an accurate image with little distortion. This enables more accurate image analysis.

公开(公告)号：US20240324309A1

公开(公告)日：2024-09-26

申请号：US18580309

申请日：2022-07-11

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshinobu ASAMI ,  Takahiro FUJIE ,  Ryo TAGASHIRA ,  Sachiko KAWAKAMI ,  Yui YOSHIYASU ,  Tomohiro KUBOTA

IPC: H10K59/122 ,  H10K59/12

CPC classification number: H10K59/122 ,  H10K59/1201

Abstract: A display apparatus with high display quality is provided. A display apparatus includes a first pixel, a second pixel provided adjacent to the first pixel, a first insulating layer, and a second insulating layer over the first insulating layer. The first pixel includes a first pixel electrode, a first EL layer covering the first pixel electrode, a common electrode over the first EL layer. The second pixel includes a second pixel electrode, a second EL layer covering the second pixel electrode, and the common electrode over the second EL layer. The first insulating layer covers part of a side surface and part of a top surface of the first EL layer and part of a side surface and part of a top surface of the second EL layer. At least part of the second insulating layer is provided to be sandwiched between an end portion of the side surface of the first EL layer and an end portion of the side surface of the second EL layer. The second insulating layer contains an acrylic resin, and the second insulating layer has a tapered side surface and a convex shaped top surface. A taper angle of the tapered side surface of the second insulating layer is less than 90°, and the common electrode overlaps with the second insulating layer.

公开(公告)号：US20240321205A1

公开(公告)日：2024-09-26

申请号：US18569779

申请日：2022-06-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuki OKAMOTO ,  Tatsuya ONUKI ,  Hidetomo KOBAYASHI ,  Munehiro KOZUMA ,  Takanori MATSUZAKI ,  Susumu KAWASHIMA ,  Yutaka OKAZAKI

IPC: G09G3/3233 ,  H01L27/088 ,  H01L27/12

CPC classification number: G09G3/3233 ,  H01L27/088 ,  H01L27/1225 ,  G09G2300/0426 ,  G09G2300/0852 ,  G09G2330/021

Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M2) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M1), the second switch (M3) and the first capacitor (C1) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M4), the second capacitor (C2) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M6) and a drain of the second transistor (M5), a gate of the second transistor is electrically connected to the fifth switch (M7), the third capacitor (C3) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element (61).

公开(公告)号：US12100795B2

公开(公告)日：2024-09-24

申请号：US16796978

申请日：2020-02-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Satoko Shitagaki ,  Satoshi Seo ,  Nobuharu Ohsawa ,  Hideko Inoue ,  Kunihiko Suzuki

IPC: H01L51/00 ,  C07D209/86 ,  C07D239/26 ,  C07D241/12 ,  C07D333/76 ,  C07D409/10 ,  C07D471/04 ,  C07F15/00 ,  C09K11/02 ,  C09K11/06 ,  H10K50/11 ,  H10K85/30 ,  H10K85/60 ,  H10K101/00 ,  H10K101/10 ,  H10K101/30

CPC classification number: H10K85/342 ,  C07D209/86 ,  C07D239/26 ,  C07D241/12 ,  C07D333/76 ,  C07D409/10 ,  C07D471/04 ,  C07F15/0033 ,  C09K11/025 ,  C09K11/06 ,  H10K50/11 ,  H10K85/631 ,  H10K85/633 ,  H10K85/636 ,  H10K85/6572 ,  H10K85/6576 ,  C09K2211/1007 ,  C09K2211/1074 ,  C09K2211/185 ,  H10K85/615 ,  H10K85/624 ,  H10K85/626 ,  H10K2101/10 ,  H10K2101/27 ,  H10K2101/30 ,  H10K2101/90

Abstract: A light-emitting element having high external quantum efficiency is provided. A light-emitting element having a long lifetime is provided. A light-emitting element is provided which includes a light-emitting layer containing a phosphorescent compound, a first organic compound, and a second organic compound between a pair of electrodes, in which a combination of the first organic compound and the second organic compound forms an exciplex (excited complex). The light-emitting element transfers energy by utilizing an overlap between the emission spectrum of the exciplex and the absorption spectrum of the phosphorescent compound and thus has high energy transfer efficiency. Therefore, a light-emitting element having high external quantum efficiency can be obtained.

公开(公告)号：US12100366B2

公开(公告)日：2024-09-24

申请号：US18212752

申请日：2023-06-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hajime Kimura ,  Atsushi Umezaki

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3648 ,  G09G3/2096 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0814 ,  G09G2300/0819 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/043

Abstract: A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

公开(公告)号：US20240313122A1

公开(公告)日：2024-09-19

申请号：US18612650

申请日：2024-03-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichi Koezuka ,  Masami Jintyou ,  Yukinori Shima

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696

Abstract: The semiconductor device includes a first insulating layer, a second insulating layer, an oxide semiconductor layer, and first to third conductive layers. The first conductive layer and the second conductive layer are connected to the oxide semiconductor layer. The second insulating layer includes a region in contact with the oxide semiconductor layer, and the third conductive layer includes a region in contact with the second insulating layer. The oxide semiconductor layer includes first to third regions. The first region and the second region are separated from each other, and the third region is located between the first region and the second region. The third region and the third conductive layer overlap with each other with the second insulating layer located therebetween. The first region and the second region include a region having a higher carbon concentration than the third region.