公开(公告)号：US20170069481A1

公开(公告)日：2017-03-09

申请号：US15254394

申请日：2016-09-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Michael A. Guillorn ,  Isaac Lauer ,  Xin Miao

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/66

CPC classification number: H01L21/0228 ,  H01L21/02603 ,  H01L21/30604 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78684 ,  H01L29/78696

Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.

Abstract translation: 包括存在于至少两个悬挂的通道结构上的栅极结构的半导体器件和存在于栅极结构的侧壁上的复合隔板。 复合间隔物可以包括沿着栅极结构的盖部分存在的包层隔离物，以及沿着悬挂的通道结构的相邻沟道半导体层之间的栅极结构的沟道部分的内部间隔物。 内部间隔件可以包括具有基本中心接缝的新月形形状。

公开(公告)号：US09589791B2

公开(公告)日：2017-03-07

申请号：US14948541

申请日：2015-11-23

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/306

CPC classification number: H01L21/02455 ,  H01L21/02538 ,  H01L21/02614 ,  H01L21/30604 ,  H01L29/0642 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.

Abstract translation: 半导体器件包括在本体层的上表面上具有体层和III-V缓冲层的晶片。 半导体器件还包括III-V缓冲层上的至少一个半导体鳍片。 半导体鳍片包括III-V沟道部分。 晶片或半导体鳍片都包括介于III-V沟道部分和III-V缓冲层之间的氧化III-V部分，以防止电流泄漏到本体层。

公开(公告)号：US20170018608A1

公开(公告)日：2017-01-19

申请号：US15093350

申请日：2016-04-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Isaac Lauer ,  Tenko Yamashita ,  Jeffrey W. Sleight

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L23/562 ,  B82Y10/00 ,  H01L21/02403 ,  H01L21/02603 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/42356 ,  H01L29/4238 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/775 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78696

Abstract: A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

公开(公告)号：US09548355B1

公开(公告)日：2017-01-17

申请号：US14748532

申请日：2015-06-24

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L23/367 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/20

CPC classification number: H01L21/02455 ,  H01L21/02538 ,  H01L21/02614 ,  H01L21/30604 ,  H01L29/0642 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.

公开(公告)号：US20170005190A1

公开(公告)日：2017-01-05

申请号：US14755029

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L21/306 ,  H01L21/02 ,  H01L21/324 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/785 ,  B82Y10/00 ,  H01L21/02057 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor wafer is provided, where the semiconductor wafer includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. Fins are formed in the semiconductor substrate and the hard mask layer. A spacer is formed on an exposed sidewall of the hard mask layer and the semiconductor substrate. The exposed portion of the semiconductor substrate is etched. A silicon-germanium layer is epitaxially formed on the exposed portions of the semiconductor substrate. An annealed silicon-germanium region is formed by a thermal annealing process within the semiconductor substrate adjacent to the silicon-germanium layer. The silicon-germanium region and the silicon-germanium layer are removed. The hard mask layer and the spacer are removed.

Abstract translation: 提供一种半导体晶片，其中半导体晶片包括半导体衬底和形成在半导体衬底上的硬掩模层。 在半导体衬底和硬掩模层中形成有金属丝。 在硬掩模层和半导体衬底的暴露侧壁上形成间隔物。 蚀刻半导体衬底的暴露部分。 在半导体衬底的暴露部分上外延形成硅 - 锗层。 通过在与硅 - 锗层相邻的半导体衬底内的热退火工艺形成退火的硅 - 锗区域。 去除硅 - 锗区和硅 - 锗层。 去除硬掩模层和间隔物。

公开(公告)号：US20170005112A1

公开(公告)日：2017-01-05

申请号：US14755204

申请日：2015-06-30

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/02 ,  H01L29/161 ,  H01L29/06

CPC classification number: H01L27/1211 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/845

Abstract: A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.

Abstract translation: 提供了包括半导体衬底，掩埋氧化物层和半导体层的绝缘体上硅衬底。 在绝缘体上硅衬底的第一区域上形成硬掩模层。 在绝缘体上硅衬底的第二区域内的半导体层上外延生长第一硅 - 锗层。 第二区域是未被硬掩模层覆盖的半导体层的至少一部分。 进行热退火处理，使得来自第一硅 - 锗层的锗原子迁移到半导体层的部分以形成第二硅 - 锗层。 去除硬掩模层。 在半导体层和第二硅 - 锗层的顶部外延生长半导体材料层，其中半导体材料层由与半导体层相同的材料构成。

公开(公告)号：US20160380049A1

公开(公告)日：2016-12-29

申请号：US14748532

申请日：2015-06-24

Applicant: International Business Machines Corporation

Inventor： Szu-Lin Cheng ,  Isaac Lauer ,  Kuen-Ting Shiu ,  Jeng-Bang Yau

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L21/02455 ,  H01L21/02538 ,  H01L21/02614 ,  H01L21/30604 ,  H01L29/0642 ,  H01L29/20 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a wafer having a bulk layer and a III-V buffer layer on an upper surface of the bulk layer. The semiconductor device further includes at least one semiconductor fin on the III-V buffer layer. The semiconductor fin includes a III-V channel portion. Either the wafer or the semiconductor fin includes an oxidized III-V portion interposed between the III-V channel portion and the III-V buffer layer to prevent current leakage to the bulk layer.

Abstract translation: 半导体器件包括在本体层的上表面上具有体层和III-V缓冲层的晶片。 半导体器件还包括III-V缓冲层上的至少一个半导体鳍片。 半导体鳍片包括III-V沟道部分。 晶片或半导体鳍片都包括介于III-V沟道部分和III-V缓冲层之间的氧化III-V部分，以防止电流泄漏到本体层。

公开(公告)号：US09449820B2

公开(公告)日：2016-09-20

申请号：US14578833

申请日：2014-12-22

Applicant: International Business Machines Corporation

Inventor： Guy M. Cohen ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/02 ,  H01L21/306 ,  H01L29/06 ,  H01L29/423 ,  H01L29/161 ,  H01L29/775 ,  H01L29/10 ,  H01L21/20 ,  H01L29/66

CPC classification number: H01L21/02603 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/2018 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1029 ,  H01L29/1033 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66477 ,  H01L29/775

Abstract: Techniques for reducing nanowire dimension and pitch are provided. In one aspect, a pitch multiplication method for nanowires includes the steps of: providing an SOI wafer having an SOI layer separated from a substrate by a BOX, wherein the SOI layer includes Si; patterning at least one nanowire in the SOI layer, wherein the at least one nanowire as-patterned has a square cross-sectional shape with flat sides; growing epitaxial SiGe on the outside of the at least one nanowire using an epitaxial process selective for growth of the epitaxial SiGe on the flat sides of the at least one nanowire; removing the at least one nanowire selective to the epitaxial SiGe, wherein the epitaxial SiGe that remains includes multiple epitaxial SiGe wires having been formed in place of the at least one nanowire that has been removed.

Abstract translation: 提供了降低纳米线尺寸和间距的技术。 一方面，用于纳米线的间距倍增方法包括以下步骤：提供具有通过BOX从衬底分离的SOI层的SOI晶片，其中所述SOI层包括Si; 在SOI层中构图至少一个纳米线，其中所述至少一个图案化的纳米线具有平坦侧面的正方形横截面形状; 在所述至少一个纳米线的外侧使用选择性地用于在所述至少一个纳米线的平坦侧上生长所述外延SiGe的外延工艺来生长外延SiGe; 去除对外延SiGe选择性的至少一个纳米线，其中保留的外延SiGe包括已经形成的多个外延SiGe线来代替已被去除的至少一个纳米线。

公开(公告)号：US09443949B1

公开(公告)日：2016-09-13

申请号：US14671173

申请日：2015-03-27

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L21/02 ,  H01L29/423 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L21/84

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/82345 ,  H01L21/84 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/401 ,  H01L29/495 ,  H01L29/66439 ,  H01L29/775

Abstract: In one aspect, a method of forming a CMOS device with multiple transistors having different Vt's is provided which includes: forming nanowires and pads on a wafer, wherein the nanowires are suspended at varying heights above an oxide layer of the wafer; and forming gate stacks of the transistors at least partially surrounding portions of each of the nanowires by: i) depositing a conformal gate dielectric around the nanowires and on the wafer beneath the nanowires; ii) depositing a conformal workfunction metal on the conformal gate dielectric around the nanowires and on the wafer beneath the nanowires, wherein an amount of the conformal workfunction metal deposited around the nanowires is varied based on the varying heights at which the nanowires are suspended over the oxide layer; and iii) depositing a conformal poly-silicon layer on the conformal workfunction metal around the nanowires and on the wafer beneath the nanowires.

Abstract translation: 一方面，提供一种形成具有不同Vt的多个晶体管的CMOS器件的方法，其包括：在晶片上形成纳米线和焊盘，其中所述纳米线在所述晶片的氧化物层上方的不同高度处悬挂; 以及通过以下步骤，至少部分地围绕所述纳米线中的每一个的所述晶体管的栅堆叠：i）在所述纳米线下方的所述纳米线周围和所述晶片上沉积共形栅极电介质; ii）在纳米线周围的纳米线周围和纳米线下方的晶片上的共形栅极电介质上沉积保形功函数金属，其中沉积在纳米线周围的一定量的共形功函数金属基于纳米线悬挂在该纳米线上的变化高度而变化 氧化层; 以及iii）在纳米线周围的纳米线周围的纳米线下方的晶片上在保形功函数金属上沉积共形多晶硅层。

公开(公告)号：US20160233320A1

公开(公告)日：2016-08-11

申请号：US15134190

申请日：2016-04-20

Applicant: International Business Machines Corporation

Inventor： Josephine B. Chang ,  Michael A. Guillorn ,  Gen P. Lauer ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC: H01L29/66 ,  H01L21/321 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/02 ,  H01L21/3213

CPC classification number: H01L29/1037 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/32115 ,  H01L21/32134 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/401 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.