公开(公告)号：US09711224B2

公开(公告)日：2017-07-18

申请号：US14657252

申请日：2015-03-13

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/08 ,  G11C16/30 ,  G11C5/02 ,  G11C8/10 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C5/02 ,  G11C5/025 ,  G11C8/10 ,  G11C16/0483

Abstract: Some embodiments include a device having an array of memory cells, a memory control unit at least partially under the array, row decoder circuitry in data communication with the memory control unit, and column decoder circuitry in data communication with the memory control unit. Some embodiments include a device having an array of memory cells, row decoder circuitry and column decoder circuitry. One of the row and column decoder circuitries is within a unit that extends at least partially under the array of memory cells and the other within a unit that is laterally outward of the array of memory cells.

公开(公告)号：US09704876B2

公开(公告)日：2017-07-11

申请号：US14511340

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/108 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  G11C8/10 ,  H01L21/02 ,  H01L27/11529 ,  H01L29/49

CPC classification number: H01L27/11582 ,  G11C8/10 ,  H01L21/02164 ,  H01L21/02532 ,  H01L21/02595 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/495 ,  H01L29/4966

Abstract: Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

公开(公告)号：US09614516B2

公开(公告)日：2017-04-04

申请号：US14501796

申请日：2014-09-30

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H03K17/16 ,  H01L23/522 ,  H01L29/423 ,  H01L29/78

CPC classification number: H03K17/162 ,  H01L23/5225 ,  H01L29/4238 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-path transistor includes an active region including a channel region and an impurity region. A gate is dielectrically separated from the channel region. A signal line is dielectrically separated from the impurity region. A conductive shield is disposed between, and dielectrically separated from, the signal line and the channel region. In some multi-path transistors, the channel region includes an extension-channel region under the conductive shield and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being in the extension-channel region to conduct substantially independent of a voltage on the signal line. In other multi-path transistors, the conductive shield is operably coupled to the impurity region and the multi-path transistor includes different conduction paths, at least one of the different conduction paths being under the conductive shield to conduct substantially independent of a voltage on the signal line.

公开(公告)号：US20160254265A1

公开(公告)日：2016-09-01

申请号：US15154335

申请日：2016-05-13

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/108 ,  H01L21/74 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/108 ,  H01L21/74 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

Abstract translation: 各种实施例包括装置和方法，包括具有交替电平的半导体材料和电介质材料的存储器阵列，其具有在交替电平上形成的存储器单元串。 一种这样的设备包括基本上形成在衬底的空腔内的存储器阵列。 外围电路可以与衬底的表面相邻并且与存储器阵列相邻地形成。 描述附加的装置和方法。

公开(公告)号：US09430417B2

公开(公告)日：2016-08-30

申请号：US14479703

申请日：2014-09-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Toru Tanzawa

IPC: G06F12/06 ,  G06F13/16

CPC classification number: G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/06 ,  G06F12/0623 ,  G06F12/14 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1052 ,  G06F2212/214 ,  G06F2212/2532 ,  Y02D10/14

Abstract: Methods of operating a memory include performing a memory access operation, obtaining an address corresponding to a subsequent memory access operation prior to stopping the memory access operation, stopping the memory access operation, sharing charge between access lines used for the memory access operation and access lines to be used for the subsequent memory access operation, and performing the subsequent memory access operation.

Abstract translation: 操作存储器的方法包括执行存储器访问操作，在停止存储器访问操作之前获得对应于后续存储器访问操作的地址，停止存储器访问操作，在用于存储器存取操作的存取线之间共享电荷和存取行 用于随后的存储器访问操作，并且执行后续存储器存取操作。

公开(公告)号：US20160163726A1

公开(公告)日：2016-06-09

申请号：US15041277

申请日：2016-02-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/249

Abstract: Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

公开(公告)号：US09318211B2

公开(公告)日：2016-04-19

申请号：US14709210

申请日：2015-05-11

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/26 ,  H01L27/115

CPC classification number: G11C16/26 ,  G11C16/04 ,  G11C16/0483 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.

公开(公告)号：US09299437B2

公开(公告)日：2016-03-29

申请号：US14222062

申请日：2014-03-21

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34

CPC classification number: G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418

Abstract: Some embodiments include apparatuses and methods having memory cells and access lines coupled to the memory cells. In one such apparatus, the access lines include a first access line and a second access line. The first access line can be adjacent to the second access line. The memory cells include a memory cell associated with the second access line. A module can be configured to apply a voltage to the first access line during an operation of accessing the memory cell associated with the second access line, and to place the second access line in a floating state during at least a portion of a time interval within the operation. Other embodiments including additional apparatus and methods are described.

Abstract translation: 一些实施例包括具有耦合到存储器单元的存储器单元和存取线的装置和方法。 在一种这样的装置中，接入线路包括第一接入线路和第二接入线路。 第一条接入线可以与第二条接入线相邻。 存储器单元包括与第二访问线相关联的存储单元。 模块可以被配置为在访问与第二接入线路相关联的存储器单元的操作期间将电压施加到第一接入线路，并且在第二接入线路的时间间隔的至少一部分期间将第二接入线路置于浮置状态 的操作。 描述包括附加装置和方法的其它实施例。

公开(公告)号：US09263460B2

公开(公告)日：2016-02-16

申请号：US14486877

申请日：2014-09-15

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: H01L21/28 ,  H01L27/115 ,  G11C16/04 ,  H01L21/04

CPC classification number: H01L27/11556 ,  G11C16/04 ,  G11C16/0408 ,  H01L21/04 ,  H01L27/11524 ,  H01L27/11551 ,  H01L29/04 ,  H01L29/16

Abstract: Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有存储单元串的装置和方法，所述存储单元串包括位于所述装置的不同级别的存储单元和耦合到所述存储单元串的选择晶体管。 在这些装置中的至少一个中，选择晶体管可以包括包括单晶半导体材料的主体区域。 描述包括附加装置和方法的其他实施例。

公开(公告)号：US09224477B2

公开(公告)日：2015-12-29

申请号：US14725619

申请日：2015-05-29

Applicant: Micron Technology, Inc.

Inventor： Toru Tanzawa

IPC: G11C5/14 ,  G11C16/04 ,  G11C16/06 ,  G11C11/56

CPC classification number: G11C16/0483 ,  G11C7/065 ,  G11C7/067 ,  G11C7/08 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/0408 ,  G11C16/0466 ,  G11C16/06 ,  G11C16/26

Abstract: Apparatuses and methods are disclosed, including an apparatus with a string of charge storage devices coupled to a common source, a first switch coupled between the string of charge storage devices and a load current source, and a second switch coupled between the load current source and the common source. Additional apparatuses and methods are described.

Abstract translation: 公开了装置和方法，包括具有耦合到公共源的电荷存储装置串的装置，耦合在电荷存储装置串和负载电流源之间的第一开关和耦合在负载电流源和 共同的来源。 描述附加的装置和方法。