公开(公告)号：US20170005043A1

公开(公告)日：2017-01-05

申请号：US14754799

申请日：2015-06-30

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Alberto PAGANI ,  Alessandro Motta

IPC: H01L23/00 ,  H01C7/10 ,  H01L23/34 ,  H01L29/36 ,  H01L27/02 ,  H01L49/02

CPC classification number: H01C7/10 ,  H01L22/34 ,  H01L23/34 ,  H01L27/0207 ,  H01L28/20 ,  H01L29/36

Abstract: An integrated circuit (IC) may include a semiconductor substrate, and a semiconductor resistor. The semiconductor resistor may include a well in the semiconductor substrate and having a first conductivity type, a first resistive region in the well having an L-shape and a second conductivity type, and a tuning element associated with the first resistive region. The IC may also include a resistance compensation circuit on the semiconductor substrate. The resistance compensation circuit may be configured to measure an initial resistance of the first resistive region, and generate a voltage at the tuning element to tune an operating resistance of the first resistive region based upon the measured initial resistance.

Abstract translation: 集成电路（IC）可以包括半导体衬底和半导体电阻器。 半导体电阻器可以包括在半导体衬底中并且具有第一导电类型的阱，阱中的第一电阻区域具有L形和第二导电类型，以及与第一电阻区域相关联的调谐元件。 IC还可以包括在半导体衬底上的电阻补偿电路。 电阻补偿电路可以被配置为测量第一电阻区域的初始电阻，并且在调谐元件处产生电压，以基于测量的初始电阻来调节第一电阻区域的工作电阻。

公开(公告)号：US20160181203A1

公开(公告)日：2016-06-23

申请号：US14865261

申请日：2015-09-25

Applicant: STMicroelectronics S.r.I.

Inventor： Andrea Paleari ,  Lorenzo Gola ,  Federica Ronchi ,  Sonia Pirotta

IPC: H01L23/532 ,  H01L21/285 ,  H01L21/288 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/2885 ,  H01L21/76804 ,  H01L21/76846 ,  H01L21/76873 ,  H01L21/76877 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electric contact structure includes a first structural layer; a second structural layer made of dielectric material extending over the first structural layer; and an intermediate layer made of conductive material extending between the first structural layer and the second structural layer. A trench extends in the second structural layer delimited laterally by a wall of the second structural layer and at the bottom by a surface region of the intermediate layer. A diffusion barrier extends in the trench covering the surface region of the intermediate layer and the wall of the second structural layer. The diffusion barrier is a TiW—TiN—TiW tri-layer.

Abstract translation: 电接触结构包括第一结构层; 由在第一结构层上延伸的介电材料制成的第二结构层; 以及在第一结构层和第二结构层之间延伸的由导电材料制成的中间层。 沟槽在第二结构层中延伸，第二结构层由第二结构层的壁横向限定，底部由中间层的表面区域延伸。 扩散屏障在覆盖中间层的表面区域和第二结构层的壁的沟槽中延伸。 扩散阻挡层是TiW-TiN-TiW三层。

公开(公告)号：US20160105017A1

公开(公告)日：2016-04-14

申请号：US14509427

申请日：2014-10-08

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.I.

Inventor： Ranajay Mallik ,  Luigi Abbatelli ,  Giuseppe Catalisano ,  Akshat Jain

IPC: H02H7/20 ,  H02H1/00

CPC classification number: H02H7/205 ,  H02H1/0007 ,  H03K17/0828 ,  H03K17/166 ,  H03K17/168 ,  H05B6/062

Abstract: A drive transistor is connected to a resonant load in a low-side drive configuration. The voltage across the conduction terminals of the drive transistor is sensed and compared to an over-voltage threshold. An over-voltage signal is asserted in response to the comparison. The drive transistor is controlled by a PWM control signal in normal mode. In response to the assertion of the over-voltage signal, the drive transistor is forced to turn on (irrespective of the PWM control signal) to relieve the over-voltage condition. Operation of the circuit may be disabled or forced into soft start mode in response to the assertion of the over-voltage signal. Additionally, the pulse width of the PWM control signal may be reduced in response to the assertion of the over-voltage signal.

Abstract translation: 驱动晶体管以低侧驱动配置连接到谐振负载。 检测驱动晶体管的导通端子两端的电压并将其与过电压阈值进行比较。 响应于比较来断言过电压信号。 驱动晶体管由正常模式下的PWM控制信号控制。 响应于过电压信号的断言，驱动晶体管被强制导通（不管PWM控制信号如何）以减轻过电压状况。 响应于过电压信号的断言，电路的操作可能被禁用或强制进入软启动模式。 此外，可以响应于过电压信号的断言而减小PWM控制信号的脉冲宽度。

公开(公告)号：US20160018461A1

公开(公告)日：2016-01-21

申请号：US14868904

申请日：2015-09-29

Applicant: STMicroelectronics S.r.I.

Inventor： Alberto PAGANI

IPC: G01R31/28

CPC classification number: G01R31/2884 ,  G01R31/2889 ,  G01R31/2891

Abstract: An electrical check executed on wafer tests for the correct positioning or alignment of the probes of a probe card on the pads or bumps of the electronic devices integrated on the wafer. A signal is applied to cause a current to circulate in at least part of a seal ring of at least one of the electronic devices. In a case where the current flows between and through multiple electronic devices, the seal rings of those electronic devices are suitably interconnected to each other by electronic structures that extend through the scribe line between electronic devices.

Abstract translation: 在晶片测试上进行电检查，以正确地定位或对准探针卡的探针在集成在晶片上的电子设备的焊盘或凸块上。 施加信号以使电流在至少一个电子设备的密封环的至少一部分中循环。 在电流在多个电子设备之间流动的情况下，这些电子设备的密封环通过在电子设备之间延伸穿过划线的电子结构彼此适当地互连。

公开(公告)号：US09240457B2

公开(公告)日：2016-01-19

申请号：US14162200

申请日：2014-01-23

Applicant: STMicroelectronics S.r.I.

Inventor： Davide Giuseppe Patti ,  Giuditta Settanni

IPC: H01L21/332 ,  H01L29/66 ,  H01L29/10 ,  H01L29/739

CPC classification number: H01L29/66333 ,  H01L29/1095 ,  H01L29/66325 ,  H01L29/7395

Abstract: An IGBT transistor includes a drift region, at least one body region housed in the drift region and having a first type of conductivity, and a conduction region, which crosses the body region in a direction perpendicular to a surface of the drift region and has the first type of conductivity and a lower resistance than the body region. The conduction region includes a plurality of implant regions, arranged at respective depths from the surface of the drift region.

Abstract translation: IGBT晶体管包括漂移区域，容纳在漂移区域中并且具有第一类型的导电性的至少一个体区和在垂直于漂移区域的表面的方向上穿过身体区域的导电区域，并且具有 第一类导电性和比身体区域更低的电阻。 导电区域包括多个植入区域，其布置在距漂移区域的表面相应的深度处。

公开(公告)号：US20160011291A1

公开(公告)日：2016-01-14

申请号：US14739195

申请日：2015-06-15

Applicant: STMICROELECTRONICS S.r.I.

Inventor： Riccardo CONDORELLI ,  Daniele MANGANO

IPC: G01R35/00 ,  G01D5/24 ,  H02J7/04 ,  G01R27/26

CPC classification number: G01R35/005 ,  G01D3/028 ,  G01D5/24 ,  G01R27/02 ,  G01R27/2605 ,  G01R35/00 ,  H02J7/045 ,  H02J7/345

Abstract: A method of interfacing a LC sensor with a control unit is provided. The control unit may include first and second contacts, where the LC sensor is connected between the first and the second contact. A capacitor is connected between the first contact and a ground. To start the oscillation of the LC sensor, the method may include during a first phase, connecting the first contact to a supply voltage and placing the second contact in a high impedance state such that the capacitor is charged through the supply voltage. During a second phase, the first contact may be placed in a high impedance state, and the second contact connected to the ground such that the capacitor transfers charge towards the LC sensor. During a third phase, the first contact and the second contact may be placed in a high impedance state so the LC sensor is able to oscillate.

Abstract translation: 提供了一种将LC传感器与控制单元接口的方法。 控制单元可以包括第一和第二触点，其中LC传感器连接在第一和第二触点之间。 电容器连接在第一触点和地之间。 为了开始LC传感器的振荡，该方法可以包括在第一阶段期间，将第一接触连接到电源电压并将第二接触置于高阻抗状态，使得电容器通过电源电压充电。 在第二阶段期间，第一接触可以被置于高阻抗状态，并且第二接触件连接到接地，使得电容器向LC传感器传送电荷。 在第三阶段期间，第一接触和第二接触可以被置于高阻抗状态，使得LC传感器能够振荡。

公开(公告)号：US09236839B2

公开(公告)日：2016-01-12

申请号：US14018291

申请日：2013-09-04

Applicant: STMicroelectronics S.r.I.

Inventor： Michele Laplaca

IPC: H03F3/26 ,  H03F3/18 ,  H03F1/02 ,  H03F3/21 ,  H03F3/30

CPC classification number: H03F3/26 ,  H03F1/0244 ,  H03F1/0277 ,  H03F3/211 ,  H03F3/3066

Abstract: A Class-G amplifier including a first and second driving transistor configured to receive an input voltage; a first supplying terminal connected to the first driving transistor to supply a first supplying voltage. The amplifier also comprises: a second supplying terminal connected to the second driving transistor to supply a second supplying voltage in absolute value higher than said first voltage; a first power transistor connected to the first driving transistor to form a first Sziklai pair structured to be activated by a first input voltage lower in absolute value than the first supplying voltage; a second power transistor connected to the second driving transistor to form a second Sziklai pair structured to be activated by an input signal comprised between the first supplying voltage and the second supplying voltage.

Abstract translation: 一种G类放大器，包括被配置为接收输入电压的第一和第二驱动晶体管; 连接到第一驱动晶体管以提供第一供电电压的第一供电端子。 放大器还包括：第二供电端子，连接到第二驱动晶体管，以提供高于所述第一电压的绝对值的第二供电电压; 连接到第一驱动晶体管的第一功率晶体管，以形成由绝对值比第一供电电压低的第一输入电压激活的第一Sziklai对; 连接到第二驱动晶体管的第二功率晶体管，以形成由第一供电电压和第二供电电压之间的输入信号激活的第二Sziklai对。

公开(公告)号：US09165237B2

公开(公告)日：2015-10-20

申请号：US14103011

申请日：2013-12-11

Applicant: STMICROELECTRONICS S.r.I. ,  STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Michele Scarlatella ,  Mariarosaria Migliaccio ,  Paolo Frallicciardi ,  Attilio Derosa

IPC: G06K19/06 ,  G06K19/077

CPC classification number: G06K19/07739 ,  Y10T29/49117

Abstract: A SIM card adapter assembly is to adapt a SIM card to a SIM slot. The adapter assembly includes a SIM card plastic support including a first portion of a predetermined thickness. The SIM card is removably attached and a second portion has an increased thickness wherein at least one adapter is removably attached.

Abstract translation: SIM卡适配器组件将SIM卡适配到SIM卡插槽。 适配器组件包括包含预定厚度的第一部分的SIM卡塑料支撑件。 SIM卡可拆卸地连接，第二部分具有增加的厚度，其中至少一个适配器可拆卸地连接。

公开(公告)号：US09125322B2

公开(公告)日：2015-09-01

申请号：US13871803

申请日：2013-04-26

Applicant: STMicroelectronics S.r.I.

Inventor： Cristiano Gianluca Stella

IPC: G06F1/20 ,  H05K5/00 ,  H05K7/20 ,  H01L23/34 ,  H01L23/48 ,  H01L31/107 ,  H01L23/02 ,  H01L21/302 ,  H01L23/367 ,  H01L23/40 ,  H05K13/00 ,  H01L23/38

CPC classification number: H05K7/20 ,  H01L21/302 ,  H01L23/02 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/38 ,  H01L23/4006 ,  H01L23/4093 ,  H01L23/48 ,  H01L2924/0002 ,  H05K7/2039 ,  H05K13/00 ,  Y10T29/49002 ,  H01L2924/00

Abstract: An electronic system includes an electronic device of through-hole mounting type comprising an insulating body for embedding at least a chip on which electronic components are integrated, a plurality of conductive leads projecting from the insulating body for said mounting, and a dissipation plate exposed from the insulating body for transferring heat from said electronic component in operation towards the outside of the insulating body. The electronic system includes a heat sink in contact with said dissipation plate for dissipating said heat. The heat sink comprises a first dissipation element, a second dissipation element, and clamping means for clamping the first dissipation element and the second dissipation element together against the insulating body of said electronic device.

Abstract translation: 一种电子系统，包括通孔安装型电子装置，该电子装置包括绝缘体，用于至少嵌入电子部件一体化的芯片，从用于所述安装的绝缘体突出的多个导电引线以及从该绝缘体露出的散热板 所述绝缘体用于将来自所述电子部件的热量在操作中传递到所述绝缘体的外部。 电子系统包括与所述散热板接触以散热所述热量的散热器。 散热器包括第一耗散元件，第二耗散元件和夹持装置，用于将第一耗散元件和第二耗散元件夹在一起抵靠所述电子器件的绝缘体。

公开(公告)号：US09025355B2

公开(公告)日：2015-05-05

申请号：US13954908

申请日：2013-07-30

Applicant: STMicroelectronics S.r.I. ,  STMicroelectronics PVT Ltd

Inventor： Fabio De Santis ,  Marco Pasotti ,  Abhishek Lal

IPC: G11C5/06 ,  G11C5/02 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。