公开(公告)号：US07220634B2

公开(公告)日：2007-05-22

申请号：US10738408

申请日：2003-12-16

Applicant: Kirk D. Prall ,  Leonard Forbes

Inventor： Kirk D. Prall ,  Leonard Forbes

IPC: H01L21/8238

CPC classification number: H01L29/7926 ,  G11C11/5692 ,  G11C16/0466 ,  G11C16/0475 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7923

Abstract: An array of memory cells configured to store at least one bit per one F2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2) and such that the programmed cell operates at reduced drain source current.

公开(公告)号：US07112542B2

公开(公告)日：2006-09-26

申请号：US10330719

申请日：2002-12-27

Applicant: Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

Inventor： Werner Juengling ,  Kirk D. Prall ,  Ravi Iyer ,  Gurtej S. Sandhu ,  Guy Blalock

IPC: H01L21/31 ,  H01L21/469 ,  H01L21/76

CPC classification number: H01L21/7682 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02167 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02362 ,  H01L21/31695 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/5329 ,  H01L2221/1047 ,  H01L2924/0002 ,  Y10T428/12014 ,  Y10T428/24149 ,  Y10T428/249921 ,  Y10T428/25 ,  Y10T428/259 ,  H01L2924/00

Abstract: Methods of forming insulating materials between conductive elements include forming a material adjacent a conductive electrical component comprising: partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. Other methods include forming a material between a pair of conductive electrical components comprising: forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components. Some embodiments include an insulating material adjacent a conductive electrical component, such material comprising a matrix and at least one void within the matrix.

Abstract translation: 在导电元件之间形成绝缘材料的方法包括形成邻近导电电气部件的材料，该材料包括：部分蒸发物质以形成邻近导电电气部件的基体，所述基体在其内具有至少一个空隙。 其他方法包括在一对导电电气部件之间形成材料，包括：在一个质量块内形成一对导电的电气部件，并由该质量块的一大片分隔; 在所述物体的宽度内形成至少一个支撑构件，所述支撑构件不包括导电互连; 以及使所述质量块的膨胀程度有效地在所述支撑构件和所述一对导电电气部件中的每一个之间形成至少一个空隙。 一些实施例包括邻近导电电气部件的绝缘材料，这种材料包括基质和基质内的至少一个空隙。

公开(公告)号：US07053444B2

公开(公告)日：2006-05-30

申请号：US11105834

申请日：2005-04-14

Applicant: Kirk D. Prall ,  Chun Chen

Inventor： Kirk D. Prall ,  Chun Chen

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/76831 ,  H01L21/76895 ,  H01L21/76897 ,  H01L27/115

Abstract: A method for forming a flash memory device having a local interconnect connecting source regions of a plurality of transistors within a sector allows for a highly selective wet etch of a dielectric region overlying the source region. An embodiment of the method comprises the use of an etch-resistant layer covering various features such as any gate oxide remaining over the source region, spacers along sidewalls of the transistor stacks, and a capping layer of the transistor. An in-process semiconductor device resulting from the inventive method is also disclosed.

公开(公告)号：US06927445B2

公开(公告)日：2005-08-09

申请号：US09921423

申请日：2001-08-02

Applicant: Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

Inventor： Randhir P. S. Thakur ,  Gordon Haller ,  Kirk D. Prall

IPC: H01L21/02 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L28/87 ,  H01L28/55 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprises a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch-resistant material, and etching the alternating layers, thereby forming a capacitor structure having corrugated sides.

Abstract translation: 一种在半导体部件上形成波纹状电容器的方法。 形成波纹状电容器的方法包括在半导体组件上具有不同蚀刻速率的一系列沉积交替层的掺杂硅玻璃，用耐蚀刻材料覆盖交替层，并蚀刻交替层，从而形成具有 波纹状。

公开(公告)号：US06750494B1

公开(公告)日：2004-06-15

申请号：US09288932

申请日：1999-04-09

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L27108

CPC classification number: H01L27/10852 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a memory cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that it fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. The removable spacer is formed of materials having higher etching selectivity relative to materials forming underlying structures. Etching of the spacer creates a buried contact opening smaller than a lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after the resist strip, leaving a sublithographic buried contact opening.

Abstract translation: 使用可去除的氧化物间隔物来减小低于光刻最小值的多晶硅字线之间的存储单元中的接触开口的尺寸。 可去除的间隔物在掩埋接触图案化和蚀刻之前被沉积。 由于字线在单元位置发散，所以可拆卸的间隔物在发散区域接触开口之间保持较小的厚度，并且由于其间较窄的间隙而间隔较大，并且间隔物被沉积以使其填充该间隙，因此在字线之间的其他位置具有更大的厚度。 由于实际的自对准接触区域由间隔壁侧壁限定，所以可拆卸间隔物减小了埋入接触尺寸。 可移除的间隔物由相对于形成底层结构的材料具有较高蚀刻选择性的材料形成。 间隔物的蚀刻产生小于光刻最小值的掩埋接触开口，因为围绕埋入接触区域的氧化硅被可移除间隔物保护。 在抗蚀剂条之后去除可移除的间隔物，留下亚光刻掩埋的接触开口。

公开(公告)号：US06282126B1

公开(公告)日：2001-08-28

申请号：US09212467

申请日：1998-12-16

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: G11C1604

CPC classification number: G11C16/0416 ,  G11C16/26

Abstract: A non-volatile memory is described which includes an array of memory cells arranged in rows and columns. A split source line architecture is implemented and uses isolation transistors located throughout the memory array to couple selected memory cells in response to an active row line signal. The isolation transistors can be provided for each row of the memory array or for a pre-determined number of memory cells, such as 8, 16 or 32. By providing a split source line and isolation transistors, read errors caused by over erased memory cells can be eliminated with minimal increase in die area.

Abstract translation: 描述了包括以行和列布置的存储器单元阵列的非易失性存储器。 实现分离源极线架构，并且使用位于整个存储器阵列中的隔离晶体管来响应于有源行线信号来耦合选定的存储器单元。 可以为存储器阵列的每一行或预定数量的存储器单元（例如8,16或32）提供隔离晶体管。通过提供分离源极线和隔离晶体管，由过度擦除的存储器单元引起的读取错误 可以消除模具面积的最小增加。

公开(公告)号：US06010953A

公开(公告)日：2000-01-04

申请号：US886707

申请日：1997-07-01

Applicant: Kirk D. Prall

Inventor： Kirk D. Prall

IPC: H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/10852 ,  H01L21/76895 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S438/947

Abstract: A removable oxide spacer is used to reduce the size of a contact opening in a memory cell between polysilicon word lines below a lithographic minimum. The removable spacer is deposited before the buried contact patterning and etching. Since word lines diverge at a cell location, the removable spacer retains a lesser thickness over the divergent area contact opening and a greater thickness elsewhere between word lines due to the more narrow gap therebetween and the spacer being deposited such that it fills the gap. The removable spacer reduces the buried contact size since the actual self-aligned contact area is defined by the spacer sidewall. The removable spacer is formed of materials having higher etching selectivity relative to materials forming underlying structures. Etching of the spacer creates a buried contact opening smaller than a lithographic minimum because silicon oxide surrounding the buried contact area is protected by the removable spacer. The removable spacer is removed after the resist strip, leaving a sublithographic buried contact opening.

Abstract translation: 使用可去除的氧化物间隔物来减小低于光刻最小值的多晶硅字线之间的存储单元中的接触开口的尺寸。 可去除的间隔物在掩埋接触图案化和蚀刻之前被沉积。 由于字线在单元位置发散，所以可拆卸的间隔物在发散区域接触开口之间保持较小的厚度，并且由于其间较窄的间隙而间隔较大，并且间隔物被沉积以使其填充该间隙，因此在字线之间的其他位置具有更大的厚度。 由于实际的自对准接触区域由间隔壁侧壁限定，所以可拆卸间隔物减小了埋入接触尺寸。 可移除的间隔物由相对于形成底层结构的材料具有较高蚀刻选择性的材料形成。 间隔物的蚀刻产生小于光刻最小值的掩埋接触开口，因为围绕埋入接触区域的氧化硅被可移除间隔物保护。 在抗蚀剂条之后去除可移除的间隔物，留下亚光刻掩埋的接触开口。

公开(公告)号：US09058857B2

公开(公告)日：2015-06-16

申请号：US13269717

申请日：2011-10-10

Applicant: Zengtao T. Liu ,  Kirk D. Prall

Inventor： Zengtao T. Liu ,  Kirk D. Prall

IPC: G11C11/21 ,  G11C8/08 ,  G11C13/00

CPC classification number: G11C13/004 ,  G11C8/08 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/0033 ,  G11C13/0038 ,  G11C2013/0054 ,  G11C2013/0057 ,  G11C2013/0083 ,  G11C2213/77

Abstract: The apparatuses and methods described herein may operate to measure a voltage difference between a selected access line and a selected sense line associated with a selected cell of a plurality of memory cells of a memory array. The voltage difference may be compared with a reference voltage specified for a memory operation. A selection voltage(s) applied to the selected cell for the memory operation may be adjusted responsive to the comparison, such as to dynamically compensate for parasitic voltage drop.

Abstract translation: 本文描述的设备和方法可以操作以测量所选择的接入线路和与存储器阵列的多个存储器单元的选定单元相关联的选择的感测线之间的电压差。 可以将电压差与为存储器操作指定的参考电压进行比较。 可以响应于比较来调整施加到用于存储器操作的所选单元的选择电压，例如动态地补偿寄生电压降。

公开(公告)号：US20130121056A1

公开(公告)日：2013-05-16

申请号：US13293353

申请日：2011-11-10

Applicant: Zengtao T. Liu ,  Kirk D. Prall ,  Mike Violette

Inventor： Zengtao T. Liu ,  Kirk D. Prall ,  Mike Violette

IPC: G11C11/00 ,  H01L21/8239

CPC classification number: H01L27/2436 ,  G11C5/063 ,  G11C8/14 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0021 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/74 ,  G11C2213/78 ,  G11C2213/79 ,  H01L27/222 ,  H01L27/228 ,  H01L27/24 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/10 ,  H01L45/065 ,  H01L45/085 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147

Abstract: The present disclosure includes methods and apparatuses that include resistive memory. A number of embodiments include a first memory cell coupled to a data line and including a first resistive storage element and a first access device, a second memory cell coupled to the data line and including a second resistive storage element and a second access device, an isolation device formed between the first access device and the second access device, a first select line coupled to the first resistive storage element, and a second select line coupled to the second resistive storage element, wherein the second select line is separate from the first select line.

Abstract translation: 本公开包括包括电阻性存储器的方法和装置。 多个实施例包括耦合到数据线并包括第一电阻存储元件和第一存取器件的第一存储器单元，耦合到数据线并包括第二电阻存储元件和第二存取器件的第二存储单元， 形成在第一存取装置和第二存取装置之间的隔离装置，耦合到第一电阻存储元件的第一选择线和耦合到第二电阻存储元件的第二选择线，其中第二选择线与第一选择线分开 线。

公开(公告)号：US20130069030A1

公开(公告)日：2013-03-21

申请号：US13234875

申请日：2011-09-16

Applicant: David H. Wells ,  D.V. Nirmal Ramaswamy ,  Kirk D. Prall

Inventor： David H. Wells ,  D.V. Nirmal Ramaswamy ,  Kirk D. Prall

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L45/085 ,  G11C2213/73 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/146

Abstract: Resistive memory cells including an integrated select device and storage element and methods of forming the same are described herein. As an example, a resistive memory cell can include a select device structure including a Schottky interface, and a storage element integrated with the select device structure such that an electrode corresponding to the Schottky interface serves as a first electrode of the storage element. The storage element can include a storage material formed between the first electrode and a second electrode.

Abstract translation: 包括集成选择装置和存储元件的电阻式存储单元及其形成方法在此描述。 作为示例，电阻式存储单元可以包括包括肖特基接口的选择器件结构和与选择器件结构集成的存储元件，使得对应于肖特基界面的电极用作存储元件的第一电极。 存储元件可以包括形成在第一电极和第二电极之间的存储材料。