公开(公告)号：US06400030B1

公开(公告)日：2002-06-04

申请号：US09583817

申请日：2000-05-30

Applicant: Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

Inventor： Fei Wang ,  Robin Cheung ,  Mark S. Chang ,  Richard J. Huang ,  Angela T. Hui

IPC: H01L2348

CPC classification number: H01L21/76897 ,  H01L21/76802

Abstract: An integrated circuit having semiconductor devices is connected by a first conductive channel damascened into a first oxide layer above the devices. A stop nitride layer, a via oxide layer, a via nitride layer, and a via resist are sequentially deposited on the first channel and the first oxide layer. The via resist is photolithographically developed with rectangular cross-section vias greater than the width of the channels and the via nitride layer is etched to the rectangular cross-section. A second channel oxide layer and a second channel resist are sequentially deposited on the via nitride layer and the exposed via oxide layer. The second channel resist is photolithographically developed with the second channels and an anisotropic oxide etch etches the second channels and rectangular box vias down to the stop nitride layer. The stop nitride layer is nitride etched in the rectangular via configuration and conductive material is damascened into the second channels and the via to be chemical-mechanical polished to form the interconnections between two levels of channels.

Abstract translation: 具有半导体器件的集成电路通过镶嵌在器件上方的第一氧化物层中的第一导电沟道连接。 在第一沟道和第一氧化物层上顺序地沉积有终止氮化物层，通孔氧化物层，通路氮化物层和通路保护层。 通孔抗蚀剂被光刻显影，具有大于通道宽度的矩形横截面通孔，并且通孔氮化物层被蚀刻到矩形横截面。 第二沟道氧化物层和第二沟道抗蚀剂依次沉积在通孔氮化物层和暴露的通孔氧化物层上。 第二通道抗蚀剂用第二通道光刻显影，并且各向异性氧化物蚀刻将第二通道和矩形盒通孔蚀刻到固定氮化物层。 阻挡氮化物层以矩形通孔结构进行氮化蚀刻，并且导电材料被镶嵌到第二通道中，并且通孔被化学机械抛光以形成两个通道级之间的互连。

公开(公告)号：US06357143B2

公开(公告)日：2002-03-19

申请号：US09909915

申请日：2001-07-20

Applicant: Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

Inventor： Ratson Morad ,  Ho Seon Shin ,  Robin Cheung ,  Igor Kogan

IPC: F26B700

CPC classification number: H01L21/67109 ,  H01L21/67115 ,  H01L21/67748

Abstract: A method and apparatus for heating and cooling a substrate. A chamber is provided that comprises a heating mechanism adapted to heat a substrate positioned proximate the heating mechanism, a cooling mechanism spaced from the heating mechanism and adapted to cool a substrate positioned proximate the cooling mechanism, and a transfer mechanism adapted to transfer a substrate between the position proximate the heating mechanism and the position proximate the cooling mechanism.

Abstract translation: 一种用于加热和冷却基底的方法和装置。 提供了一种室，其包括适于加热位于加热机构附近的基板的加热机构，与加热机构间隔开并适于冷却位于冷却机构附近的基板的冷却机构，以及适于将基板 靠近加热机构的位置和靠近冷却机构的位置。

公开(公告)号：US06245670B1

公开(公告)日：2001-06-12

申请号：US09253480

申请日：1999-02-19

Applicant: Robin Cheung ,  Sergey Lopatin

Inventor： Robin Cheung ,  Sergey Lopatin

IPC: H01L214763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76877

Abstract: A method for effectively filling a dual damascene opening having a via hole and a trench that are contiguous openings uses a two step deposition process. The method includes a step of filling the via hole by electroless deposition of a first conductive material into the via hole. A second conductive material is at a bottom wall of the via hole, and the second conductive material at the bottom wall of the via hole acts as an autocatalytic surface during the electroless deposition of the first conductive material within the via hole. The method also includes the step of depositing a seed layer of a third conductive material to cover walls of the trench and includes the step of filling the trench by electroplating deposition of the third conductive material from the seed layer into the trench. The present invention may be used to particular advantage for small geometry integrated circuits when the conductive material filling the via hole and the trench is copper. By first filling the via hole using electroless deposition, void formation and poor via contact is prevented. In addition, the more widely available and easily manufacturable electroplating deposition process is still used for filling the trench.

Abstract translation: 一种用于有效地填充具有通孔和作为连续开口的沟槽的双镶嵌开口的方法使用两步沉积工艺。 该方法包括通过将第一导电材料无电沉积到通孔中来填充通孔的步骤。 第二导电材料位于通孔的底壁处，并且在第一导电材料在通孔内的无电沉积期间，通孔的底壁处的第二导电材料用作自催化表面。 该方法还包括沉积第三导电材料的种子层以覆盖沟槽的壁的步骤，并且包括通过电镀将第三导电材料从晶种层沉积到沟槽中来填充沟槽的步骤。 当填充通孔和沟槽的导电材料是铜时，本发明可以用于小几何形状集成电路的特别有利。 通过首先使用无电沉积填充通孔，防止空隙形成和差的通孔接触。 此外，仍然使用更广泛可用且容易制造的电镀沉积工艺来填充沟槽。

公开(公告)号：US6083842A

公开(公告)日：2000-07-04

申请号：US253479

申请日：1999-02-19

Applicant: Robin Cheung ,  Sergey Lopatin

Inventor： Robin Cheung ,  Sergey Lopatin

IPC: H01L21/768 ,  H01L21/302

CPC classification number: H01L21/76852 ,  H01L21/76843 ,  H01L21/76885

Abstract: A method for efficiently fabricating a via plug having high aspect ratio within an insulating layer with a diffusion barrier layer effectively surrounding the via plug. The method includes the steps of depositing a via photoresist layer over a first metal line of a first conductive material and etching a via hole in the via photoresist layer. The first conductive material of the first metal line is exposed at a bottom wall of the via hole. A via plug of a second conductive material is deposited into the via hole, and the via plug makes a conductive path with the first metal line. The via photoresist layer is then removed such that any side wall of the via plug is exposed. A first diffusion barrier layer is then deposited onto any exposed surface of the second conductive material of the via plug. A via insulating layer is then spin-coated to surround the via plug and a trench insulating layer is also deposited over the via insulating layer. A trench is then etched over the via plug having the first diffusion barrier layer, and the via plug with the first diffusion barrier layer is exposed as part of a bottom wall of the trench. A second diffusion barrier layer is then deposited onto the walls of the trench, and a third conductive material is deposited into the trench to form a second metal line. The second metal line makes a conductive path with the second conductive material of the via plug. Thus, the present invention avoids the prior art method of depositing a diffusion barrier layer into the via hole within a via insulating layer before filling the via hole with the via plug. With the present invention, a via plug with high aspect ratio may be efficiently formed with the diffusion barrier layer effectively surrounding the via plug.

Abstract translation: 一种用于在绝缘层内有效地制造具有高纵横比的通孔的方法，其中扩散阻挡层有效围绕通孔塞。 该方法包括以下步骤：在第一导电材料的第一金属线上沉积通孔光致抗蚀剂层，并蚀刻通孔光致抗蚀剂层中的通孔。 第一金属线的第一导电材料暴露在通孔的底壁处。 第二导电材料的通孔插入到通孔中，并且通孔插头与第一金属线形成导电路径。 然后去除通孔光致抗蚀剂层，使得通孔塞的任何侧壁暴露。 然后将第一扩散阻挡层沉积到通孔塞的第二导电材料的任何暴露的表面上。 然后将通孔绝缘层旋涂以包围通孔塞，并且沟槽绝缘层也沉积在通孔绝缘层上。 然后在具有第一扩散阻挡层的通孔上蚀刻沟槽，并且具有第一扩散阻挡层的通孔插塞作为沟槽底壁的一部分暴露。 然后将第二扩散阻挡层沉积在沟槽的壁上，并且将第三导电材料沉积到沟槽中以形成第二金属线。 第二金属线与通孔塞的第二导电材料形成导电路径。 因此，本发明避免了在使用通孔插塞填充通孔之前在通孔绝缘层中的通孔中沉积扩散阻挡层的现有技术方法。 利用本发明，可以有效地形成具有高纵横比的通孔，扩散阻挡层有效地围绕过孔塞。

公开(公告)号：US6048802A

公开(公告)日：2000-04-11

申请号：US905978

申请日：1997-08-05

Applicant: Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

Inventor： Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

CPC classification number: H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After all of the conductive lines have received a deposit of conformal insulating material and a flowable insulating material, the composite insulating materials are removed, preferably by etching, from those pairs of conductive lines with a gap of about 0.5 microns or less. Now, a nonconformal insulating material with a poor step function is deposited and creates a large void in the open gaps of 0.5 microns or less. After creating the void, the deposition continues and is planarized at the desired composite thickness of insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with the gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在所有导电线都已经接收到保形膜 绝缘材料和可流动的绝缘材料，优选通过蚀刻从具有约0.5微米或更小的间隙的那对导电线去除复合绝缘材料。 现在，沉积具有差的阶梯函数的非共形绝缘材料，并且在0.5微米或更小的开放间隙中产生大的空隙。 在形成空隙之后，沉积继续并且在所需的绝缘复合厚度下被平坦化。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所得到的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，导电线对之间的绝缘介电常数为0.5或更小的间隙，与空隙结合为至少约3 或更低，并且所有剩余间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

公开(公告)号：US6033982A

公开(公告)日：2000-03-07

申请号：US149208

申请日：1998-09-08

Applicant: Sergey Lopatin ,  Robin Cheung

Inventor： Sergey Lopatin ,  Robin Cheung

IPC: H01L21/316 ,  H01L21/768 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/326

CPC classification number: H01L21/76888 ,  H01L21/31687 ,  H01L21/76885 ,  Y10S257/915 ,  Y10S428/901 ,  Y10T428/12493 ,  Y10T428/12597 ,  Y10T428/12611

Abstract: A method of forming a conductive line structure is provided. An adhesion layer is formed on a substrate surface. A seed layer is formed on the adhesion layer. A conductor is formed on the seed layer to form a partially complete structure. The partially complete structure is exposed to an electrolyte and undergoes an anodization process. At least a portion of the seed layer and a portion of the conductor are transformed to seed layer metal oxide and conductor metal oxide, respectively. At least a portion of the adhesion layer is transformed to an adhesion layer metal oxide and a further portion of the conductor is transformed to the conductor metal oxide. An outer metal layer is formed over the seed layer metal oxide and the conductor metal oxide.

Abstract translation: 提供一种形成导线结构的方法。 在基板表面上形成粘合层。 种子层形成在粘合层上。 在种子层上形成导体以形成部分完整的结构。 部分完整的结构暴露于电解质并进行阳极氧化处理。 种子层和导体的一部分的至少一部分分别转化为晶种层金属氧化物和导体金属氧化物。 粘合层的至少一部分被转化为粘合层金属氧化物，并且导体的另一部分转变为导体金属氧化物。 在种子层金属氧化物和导体金属氧化物上形成外部金属层。

公开(公告)号：US5968333A

公开(公告)日：1999-10-19

申请号：US55876

申请日：1998-04-07

Applicant: Takeshi Nogami ,  Valery Dubin ,  Robin Cheung

Inventor： Takeshi Nogami ,  Valery Dubin ,  Robin Cheung

IPC: C23C14/02 ,  C23C28/02 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H05K3/04 ,  H05K3/10 ,  H05K3/38 ,  H05K3/42 ,  C25D5/02 ,  C25D5/56

CPC classification number: H01L21/76873 ,  C23C28/023 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76877 ,  H05K3/423 ,  H05K2201/0376 ,  H05K2201/09563 ,  H05K2201/09845 ,  H05K3/045 ,  H05K3/107 ,  H05K3/388

Abstract: Copper or a copper alloy is electroplated to fill via/contact holes and/or trenches in a dielectric layer. A barrier layer is initially deposited on the dielectric layer lining the hole/trench. A thin conformal layer of copper or a copper alloy is sputter deposited on the barrier layer outside the hole/trench. Copper or a copper alloy is then electroplated on the conformal copper or copper alloy layer and filling the hole/trench. During electroplating, the barrier layer functions as a seed layer within the hole/trench while the sputter deposited conformal copper or copper alloy layer enhances the flow of electrons from the wafer edge inwardly to provide a favorable deposition rate.

Abstract translation: 电镀铜或铜合金以填充电介质层中的通孔/接触孔和/或沟槽。 最初在衬在孔/沟上的电介质层上沉积阻挡层。 铜或铜合金的薄保形层溅射沉积在孔/沟槽外的势垒层上。 然后将铜或铜合金电镀在保形铜或铜合金层上并填充孔/沟槽。 在电镀期间，阻挡层用作孔/沟内的种子层，而溅射沉积的共形铜或铜合金层可以使电子从晶片边缘向内流动，从而提供有利的沉积速率。

公开(公告)号：US5955786A

公开(公告)日：1999-09-21

申请号：US481906

申请日：1995-06-07

Applicant: Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

Inventor： Steven Avanzino ,  Darrell Erb ,  Robin Cheung ,  Rich Klein

IPC: H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/02164 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/31612 ,  H01L21/7682 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposition of the nonconformal source material is stopped and a flowable insulating material, such as spin on glass, is coated on nonconformal insulating material to fill the remaining gaps. After etching the surfaces of the nonconformal and flowable insulating materials, another insulating layer is deposited and planarized to the desired overall thickness of the insulation. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines. The resulting structure of the interconnection level comprises a layer of insulation between and on the conductive lines with the dielectric constant of the insulation between the pairs of conductive lines with gap of 0.5 or less being, in combination with the void, at least about 3 or lower, and substantially all of the remaining gaps are filled with the flowable insulating material and are void free with a composite dielectric constant of greater than about 3.5.

Abstract translation: 在这些导电线对之间形成低介电绝缘的方法，该集成电路的互连级别具有约0.5微米或更小的间隙，通过沉积具有差的绝缘材料的步进功能的非共形源，例如硅烷 （SiH4）作为二氧化硅（SiO 2）的硅（Si）源，以在间隙中产生介电常数略大于1的大空隙。在0.5微米或更小的空隙形成之后 间隙，停止非共形源材料的沉积，并且将可流动的绝缘材料（例如玻璃上的旋涂）涂覆在非共形绝缘材料上以填充剩余的间隙。 在蚀刻非共形和可流动的绝缘材料的表面之后，另外的绝缘层被沉积并平坦化到所需绝缘体的总厚度。 或者，首先在导电线上沉积薄的共形绝缘层作为衬垫。 所形成的互连级别的结构包括在导电线之间和之间的导电层之间的绝缘层，其中间隔为0.5或更小的导电线对之间的绝缘体的介电常数与空隙结合为至少约3或 较低且基本上所有剩余的间隙都填充有可流动绝缘材料，并且无复合介电常数大于约3.5。

公开(公告)号：US5675186A

公开(公告)日：1997-10-07

申请号：US672683

申请日：1996-06-28

Applicant: Lewis Shen ,  Sheshadri Ramaswami ,  Mark Chang ,  Robin Cheung

Inventor： Lewis Shen ,  Sheshadri Ramaswami ,  Mark Chang ,  Robin Cheung

IPC: H01L23/52 ,  H01L21/3205 ,  H01L23/532 ,  H01L29/43

CPC classification number: H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

Abstract: A Ti.sub.x N.sub.y layer, not necessarily stoichiometric, is interposed between a titanium or aluminum interconnect layer to improve adhesion and prevent re-entrant undercutting and lifting of the interconnect layer during the process of patterning and plasma etching to form interconnect lines on a substrate, such as an oxide.

Abstract translation: 不需要化学计量的TixNy层被插入在钛或铝互连层之间，以在图案化和等离子体蚀刻的过程中提高粘附性并防止互连层的倒入和提升，以在衬底上形成互连线，例如 氧化物。

公开(公告)号：US5639691A

公开(公告)日：1997-06-17

申请号：US590781

申请日：1996-01-24

Applicant: Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

Inventor： Richard K. Klein ,  Darrell M. Erb ,  Steven Avanzino ,  Robin Cheung ,  Scott Luning ,  Bryan Tracy ,  Subhash Gupta ,  Ming-Ren Lin

IPC: H01L21/768 ,  H01L21/283

CPC classification number: H01L21/76805 ,  H01L21/76877 ,  Y10S257/915 ,  Y10S438/927

Abstract: A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the via. A barrier layer is provided between the reservoir and an insulating layer to prevent the pellet from diffusing into the insulating layer. The pellet can be formed by selective deposition or by etching a conformal layer. The conformal layer can be deposited by sputtering, collimated sputtering, chemical vapor deposition (CVD), dipping, evaporating, or by other means. The barrier layer and pellet may be etched by anisotropic dry etching, plasma-assisted etching, or other layer removal techniques.