公开(公告)号：US20050003745A1

公开(公告)日：2005-01-06

申请号：US10866040

申请日：2004-06-14

Applicant: Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

Inventor： Akihiro Tanoue ,  Yoshiharu Hidaka ,  Shin Hashimoto

IPC: H01L21/304 ,  B24B37/04 ,  B24B57/02 ,  B24B1/00

CPC classification number: B24B37/04 ,  B24B57/02

Abstract: A slurry feeding apparatus includes closed slurry bottle, piping, wet nitrogen generator, wet nitrogen supply pipe, suction and spray nozzles, temperature regulator, flow rate control valves, slurry delivery pump and controller for controlling the operation and flow rate of the slurry delivery pump. While a wafer is being polished by a CMP polisher, the controller continuously operates the pump. On the other hand, while the polisher is idling, the controller starts and stops the pump intermittently at regular intervals. No stirrer like a propeller is inserted into the slurry bottle, but the slurry is stirred up by spraying the slurry through the spray nozzle.

Abstract translation: 浆料输送装置包括封闭的浆液瓶，管道，湿氮发生器，湿氮供给管，抽吸喷嘴，温度调节器，流量控制阀，浆料输送泵和控制器，用于控制浆料输送泵的操作和流速 。 当晶圆被CMP抛光机抛光时，控制器连续地操作泵。 另一方面，当抛光机空转时，控制器会间歇地间歇地启动和停止泵。 没有像螺旋桨那样的搅拌器被插入到浆料瓶中，但是通过喷雾喷雾浆料来搅拌浆料。

公开(公告)号：US06323663B1

公开(公告)日：2001-11-27

申请号：US09396884

申请日：1999-09-16

Applicant: Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

Inventor： Yoshirou Nakata ,  Toshio Yamada ,  Atsushi Fujiwara ,  Isao Miyanaga ,  Shin Hashimoto ,  Yukiharu Uraoka ,  Yasushi Okuda ,  Kenzou Hatada

IPC: G01R1073

CPC classification number: G01R31/2886 ,  G01R1/0491 ,  G01R31/2831 ,  G01R31/2867

Abstract: A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Abstract translation: 提供了一种保持板，其具有多个用于测试半导体芯片的集成电路端子的半导体晶片，与具有电连接到其相应的集成电路端子的多个探针端子的探针片相对。 具有与多个探针端子电连接的布线的绝缘基板设置在与保持板相对的探针片上。 在探针片和绝缘基片之间插入弹性部件。 保持板和探针片的关系使得由保持板保持的半导体晶片的每个集成电路端子电连接到其对应的探针片的探针端子。

公开(公告)号：US06308316B1

公开(公告)日：2001-10-23

申请号：US09004505

申请日：1998-01-08

Applicant: Shin Hashimoto ,  Reiji Masaki

Inventor： Shin Hashimoto ,  Reiji Masaki

IPC: G06F945

CPC classification number: G06F11/3404

Abstract: An apparatus analyzes the operations of a parallel processing system. The parallel processing system has a serial processing state, a redundant parallel processing state, and a parallel processing state. The apparatus carries out an interrupt process to provide information about the program executing conditions of the parallel processing system. This apparatus efficiently provides information about parallel processing carried out in a multiprocessor system.

Abstract translation: 一种装置分析并行处理系统的操作。 并行处理系统具有串行处理状态，冗余并行处理状态和并行处理状态。 该装置执行中断处理以提供关于并行处理系统的程序执行条件的信息。 该装置有效地提供关于在多处理器系统中执行的并行处理的信息。

公开(公告)号：US06291350B1

公开(公告)日：2001-09-18

申请号：US09127819

申请日：1998-08-03

Applicant: Shin Hashimoto ,  Yuichi Miyoshi

Inventor： Shin Hashimoto ,  Yuichi Miyoshi

IPC: H01L21302

CPC classification number: B24B37/04 ,  B24B1/04 ,  B24B57/02

Abstract: An ultrasonic transmitting unit transmits an ultrasonic wave to a slurry supply pipe. A polishing slurry is conveyed under pressure from a slurry supply tank to a slurry outlet via the slurry supply pipe and supplied from the slurry outlet to a surface of a polishing cloth. A wafer carrier holding a semiconductor wafer presses a surface of the semiconductor wafer against the surface of the polishing cloth coated with the polishing slurry and moves the semiconductor wafer relative to the polishing cloth to polish the surface of the semiconductor wafer. A discharged slurry flown out of the surface of the polishing cloth is discharged via a discharged slurry pipe. The application of the ultrasonic wave allows abrasive particles agglomerated in the polishing slurry in the slurry supply pipe to be re-dispersed into individual forms in the polishing slurry.

Abstract translation: 超声波发送单元向浆料供给管发送超声波。 抛光浆料在压力下通过浆料供给管从浆料供应罐输送到浆料出口，并从浆料出口供给到抛光布的表面。 保持半导体晶片的晶片载体将覆盖有抛光浆料的抛光布的表面压在半导体晶片的表面上，并使半导体晶片相对于抛光布移动以抛光半导体晶片的表面。 从抛光布表面流出的排出的浆料通过排出的浆料管排出。 超声波的应用允许在浆料供给管中的研磨浆中附着的磨料颗粒在抛光浆料中再分散成各种形式。

公开(公告)号：US5825193A

公开(公告)日：1998-10-20

申请号：US575735

申请日：1995-12-18

Applicant: Yoshiro Nakata ,  Shin Hashimoto ,  Isao Miyanaga

Inventor： Yoshiro Nakata ,  Shin Hashimoto ,  Isao Miyanaga

IPC: G01R31/28 ,  H01L21/66 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04

CPC classification number: G01R31/2884 ,  G01R31/2849

Abstract: A semiconductor integrated circuit apparatus having a plurality of semiconductor integrated circuit devices, each of the plurality of semiconductor devices including a semiconductor integrated circuit formed on a semiconductor substrate, a reference voltage input terminal formed on the semiconductor substrate which is operative for receiving a reference voltage input from outside of the semiconductor substrate, and a burn-in voltage control circuit formed on the semiconductor substrate operative for receiving the reference voltage which is output from the reference voltage input terminal. The burn-in voltage control circuit generates a burn-in supply voltage which is input to the semiconductor integrated circuit, and also maintains the burn-in supply voltage at the reference voltage level such that each of the integrated circuits receives a burn-in supply voltage having the same voltage level.

Abstract translation: 一种具有多个半导体集成电路器件的半导体集成电路器件，所述多个半导体器件中的每一个包括形成在半导体衬底上的半导体集成电路，形成在所述半导体衬底上的参考电压输入端子，所述参考电压输入端子用于接收参考电压 从半导体衬底的外部输入，以及形成在半导体衬底上的老化电压控制电路，用于接收从参考电压输入端子输出的参考电压。 老化电压控制电路产生输入到半导体集成电路的老化电源电压，并且将老化电源电压维持在参考电压电平，使得每个集成电路接收老化电源 电压具有相同的电压电平。

公开(公告)号：US5795828A

公开(公告)日：1998-08-18

申请号：US675667

申请日：1996-07-03

Applicant: Masayuki Endo ,  Akemi Kawaguchi ,  Mikio Nishio ,  Shin Hashimoto

Inventor： Masayuki Endo ,  Akemi Kawaguchi ,  Mikio Nishio ,  Shin Hashimoto

IPC: C23C18/34 ,  C23C18/40 ,  C23C18/44 ,  H01L21/44

CPC classification number: C23C18/40 ,  C23C18/34 ,  C23C18/44

Abstract: A contact hole and a wiring groove are formed in an insulating layer formed on a semiconductor substrate. A silver layer is formed inside of the contact hole and the wiring groove and on the insulating layer with the use of an electroless plating bath comprising: silver nitrate containing silver ions; tartaric acid serving as a reducing agent of the silver ions; ethylenediamine serving as a complexing agent of the silver ions; and metallic ions of tetramethylammoniumhydroxide serving as a pH control agent. Then, the silver layer on the insulating layer is removed by a chemical and mechanical polishing method such that an embedded wiring is formed in each of the contact hole and the wiring groove.

Abstract translation: 在半导体衬底上形成的绝缘层中形成接触孔和布线槽。 通过使用含有银离子的硝酸银的化学镀浴，在接触孔和布线槽内部和绝缘层上形成银层; 酒石酸作为银离子的还原剂; 乙二胺作为银离子的络合剂; 和作为pH调节剂的四甲基氢氧化铵的金属离子。 然后，通过化学和机械抛光方法去除绝缘层上的银层，使得在每个接触孔和布线槽中形成嵌入的布线。

公开(公告)号：US5296719A

公开(公告)日：1994-03-22

申请号：US915311

申请日：1992-07-20

Applicant: Yoshihiko Hirai ,  Juro Yasui ,  Yasuaki Terui ,  Kiyoshi Morimoto ,  Atsuo Wada ,  Kenji Okada ,  Shin Hashimoto ,  Shinji Odanaka ,  Masaaki Niwa ,  Kaoru Inoue

Inventor： Yoshihiko Hirai ,  Juro Yasui ,  Yasuaki Terui ,  Kiyoshi Morimoto ,  Atsuo Wada ,  Kenji Okada ,  Shin Hashimoto ,  Shinji Odanaka ,  Masaaki Niwa ,  Kaoru Inoue

IPC: H01L21/265 ,  H01L21/335 ,  H01L29/12 ,  H01L29/423 ,  H01L29/49 ,  H01L21/308 ,  H01L27/08

CPC classification number: H01L29/4908 ,  B82Y10/00 ,  H01L21/26586 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/78 ,  Y10S438/962

Abstract: A quantum wire is formed at the top of triangular protrusion of silicon substrate. A quantum wire is isolated from the substrate by silicon oxide layers. A quantum wire is isolated from the substrate by impurity layers of a conduction type different from that of the substrate. An insulator film and a gate electrode are formed at the edge of triangular protrusion of a silicon substrate, and a quantum wire is induced by applying a voltage to the gate electrode. A quantum wire structure is fabricated by forming saw-tooth-like protrusions having (111) side planes by performing anisotropic crystalline etching and by oxidizing the silicon substrate with use of the oxide protection film to remain only around the top of the protrusions unoxidized. In another method, an oxide film is formed except around the top of the protrusions whereby a quantum wire is formed at the unoxidized region. In a different method, impurity layers are formed except around the top of the protrusions by ion implantation.

Abstract translation: 量子线形成在硅衬底的三角形突起的顶部。 量子线通过氧化硅层与衬底隔离。 通过不同于衬底的导电类型的杂质层将量子线与衬底隔离。 绝缘膜和栅电极形成在硅衬底的三角形突起的边缘处，并且通过向栅电极施加电压来诱导量子线。 通过形成具有（111）侧面的锯齿形突起，通过进行各向异性的结晶蚀刻，并且通过使用氧化物保护膜氧化硅衬底而制成量子线结构，仅保留在未氧化的突起的顶部。 在另一种方法中，除了突起的顶部之外形成氧化物膜，从而在未氧化区域形成量子线。 在不同的方法中，通过离子注入除了突起的顶部之外形成杂质层。

公开(公告)号：US08653561B2

公开(公告)日：2014-02-18

申请号：US13038071

申请日：2011-03-01

Applicant: Shin Hashimoto ,  Katsushi Akita ,  Yoshiyuki Yamamoto ,  Masaaki Kuzuhara ,  Norimasa Yafune

Inventor： Shin Hashimoto ,  Katsushi Akita ,  Yoshiyuki Yamamoto ,  Masaaki Kuzuhara ,  Norimasa Yafune

IPC: H01L21/02 ,  H01L29/778 ,  H01L21/335

CPC classification number: H01L29/66462 ,  H01L21/0237 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/7787

Abstract: A III-nitride semiconductor electronic device comprises a semiconductor laminate provided on a primary surface of a substrate, a first electrode in contact with the semiconductor laminate, and a second electrode. The semiconductor laminate includes a channel layer and a barrier layer making a junction with the channel layer. The channel layer comprises first III-nitride semiconductor containing aluminum as a Group III constituent element, and the barrier layer comprises second III-nitride semiconductor containing aluminum as a Group III constituent element. The semiconductor laminate including first, second and third regions arranged along the primary surface, and the third region is located between the first region and the second region. The barrier layer includes first to third portions included in the first to third regions, respectively. A concentration of impurity in the first portion is the same as that of impurity in the second portion, and the first and second electrodes is provided on the first and second regions, respectively. The first electrode includes a drain electrode or a source electrode. An aluminum composition of the first III-nitride semiconductor is not less than 0.16, and a bandgap of the second III-nitride semiconductor being larger than that of the first III-nitride semiconductor.

Abstract translation: III族氮化物半导体电子器件包括设置在衬底的主表面上的半导体层叠体，与半导体层叠体接触的第一电极和第二电极。 半导体层叠体包括沟道层和与沟道层形成结的阻挡层。 沟道层包括含有铝作为III族构成元素的第一III族氮化物半导体，并且阻挡层包含含有铝作为III族构成元素的第二III族氮化物半导体。 包括沿主表面布置的第一，第二和第三区域以及第三区域的半导体层叠体位于第一区域和第二区域之间。 阻挡层包括分别包括在第一至第三区域中的第一至第三部分。 第一部分中的杂质浓度与第二部分中的杂质浓度相同，第一和第二电极分别设置在第一和第二区域上。 第一电极包括漏电极或源电极。 第一III族氮化物半导体的铝组成不小于0.16，并且第二III族氮化物半导体的带隙大于第一III族氮化物半导体的带隙。

公开(公告)号：US08541816B2

公开(公告)日：2013-09-24

申请号：US12740770

申请日：2008-10-28

Applicant: Shin Hashimoto ,  Tatsuya Tanabe

Inventor： Shin Hashimoto ,  Tatsuya Tanabe

IPC: H01L21/338

CPC classification number: H01L29/205 ,  H01L21/02378 ,  H01L21/02389 ,  H01L21/0242 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/7787 ,  H01L29/872

Abstract: In a group III nitride hetero junction transistor 11a, a second AlY1InY2Ga1-Y1-Y2N layer 15 forms a hetero junction 21 with a first AlX1InX2Ga1-X1-X2N layer 13a. A first electrode 17 forms a Schottky junction with the first AlX1InX2Ga1-X1-X2N layer 13a. The first AlX1InX2Ga1-X1-X2N layer 13a and the second AlY1InY2Ga1-Y1-Y2N layer 15 are provided over a substrate 23. The electrodes 17a, 18a, and 19a include a source electrode, a gate electrode, and a drain electrode, respectively. The carbon concentration NC13 in the first AlX1InX2Ga1-X1-X2N layer 13a is less than 1×1017 cm−3. The dislocation density D in the second AlY1InY2Ga1-Y1-Y2N layer 15 is 1×108 cm−2. The hetero junction 21 generates a two-dimensional electron gas layer 25. These provide a low-loss gallium nitride based electronic device.

Abstract translation: 在III族氮化物异质结晶体管11a中，第二AlY1InY2Ga1-Y1-Y2N层15与第一AlX1InX2Ga1-X1-X2N层13a形成异质结21。 第一电极17与第一AlX1InX2Ga1-X1-X2N层13a形成肖特基结。 第一AlX1InX2Ga1-X1-X2N层13a和第二AlY1InY2Ga1-Y1-Y2N层15设置在衬底23上。电极17a，18a和19a分别包括源电极，栅极电极和漏电极。 第一AlX1InX2Ga1-X1-X2N层13a中的碳浓度NC13小于1×1017cm-3。 第二AlY1InY2Ga1-Y1-Y2N层15中的位错密度D为1×108cm-2。 异质结21产生二维电子气体层25.这些提供了一种低损耗氮化镓基电子器件。

公开(公告)号：US08076736B2

公开(公告)日：2011-12-13

申请号：US12518124

申请日：2008-02-12

Applicant: Masashi Hayashi ,  Shin Hashimoto

Inventor： Masashi Hayashi ,  Shin Hashimoto

IPC: H01L29/78

CPC classification number: H01L29/7802 ,  H01L21/0485 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/4975 ,  H01L29/66068

Abstract: A semiconductor device according to the present invention comprises a silicon carbide semiconductor substrate (1) including a silicon carbide layer (2); a high-concentration impurity region (4) provided in the silicon carbide layer (2); an ohmic electrode (9) electrically connected with the high-concentration impurity region (4); a channel region electrically connected with the high-concentration impurity region; a gate insulating layer (14) provided on the channel region; and a gate electrode (7) provided on the gate insulating layer (14). The ohmic electrode (9) contains an alloy of titanium, silicon and carbon, and the gate electrode (7) contains titanium silicide.

Abstract translation: 根据本发明的半导体器件包括：碳化硅半导体衬底（1），其包括碳化硅层（2）; 设置在碳化硅层（2）中的高浓度杂质区（4）; 与高浓度杂质区（4）电连接的欧姆电极（9）。 与高浓度杂质区电连接的沟道区域; 设置在所述沟道区上的栅极绝缘层（14） 以及设置在所述栅极绝缘层（14）上的栅电极（7）。 欧姆电极（9）含有钛，硅和碳的合金，栅电极（7）含有硅化钛。