公开(公告)号：US20080042282A1

公开(公告)日：2008-02-21

申请号：US11872295

申请日：2007-10-15

申请人： Tatsuyuki SAITO ,  Naohumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

发明人： Tatsuyuki SAITO ,  Naohumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

IPC分类号： H01L21/4763 ,  H01L23/48

CPC分类号： H01L21/76849 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/53295 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13

摘要： A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.

摘要翻译： 在半导体衬底上形成的氧化硅膜上形成有用于配线的沟槽的氧化硅膜和氮化硅膜，依次形成阻挡层和铜膜。 此后，从用于布线的槽的外侧除去阻挡层和铜膜，从而形成布线。 钨选择性地或优先地生长在布线上以在布线上选择性地形成钨膜。 铜膜形成后，可以进行氢处理。 在形成布线之后，可以用能够除去异物或污染金属的清洁溶液来清洁半导体衬底。 形成布线后，进行氢的处理。

公开(公告)号：US20060289917A1

公开(公告)日：2006-12-28

申请号：US11473229

申请日：2006-06-23

申请人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshihiro Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

发明人： Tsuyoshi Fujiwara ,  Toshinori Imai ,  Takeshi Saikawa ,  Yoshihiro Kawasaki ,  Mitsuhiro Toya ,  Shunji Mori ,  Yoshiyuki Okabe

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/87

摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

摘要翻译： 提供了一种能够减小电容器的寄生电容同时减小电容器所占空间的技术。 通过在由下电极构成的电容器，电容绝缘膜和中间电极上形成电容器，由中间电极，另一电容绝缘膜和上电极构成的另一电容器形成堆叠结构。 由于中间电极具有台阶差，所以在电容器形成区域以外的区域中，中间电极和下部电极之间的距离以及中间电极和上部电极之间的距离变得比电容器形成区域的大。 例如，下电极与电容器形成区域中的电容绝缘膜直接接触，而在电容器形成区域以外的区域中，下电极不与电容器绝缘膜直接接触。

公开(公告)号：US06908847B2

公开(公告)日：2005-06-21

申请号：US10329831

申请日：2002-12-27

申请人： Tatsuyuki Saito ,  Naofumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

发明人： Tatsuyuki Saito ,  Naofumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

IPC分类号： H01L29/43 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/84 ,  H01L23/532 ,  H01L27/12 ,  H01L29/423 ,  H01L29/49 ,  H01L21/4763

CPC分类号： H01L21/76844 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76838 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/84 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/5329 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has first interlayer insulating film having a wiring trench; a wiring portion having a first barrier metal layer formed over side walls and bottom surface of the wiring trench, a first conductor layer formed over the first barrier metal layer to embed the wiring trench, and a capping barrier metal film formed over the first conductor layer; second interlayer insulating film formed over the first interlayer insulating film and having a connecting hole; and a connecting portion having a second barrier metal layer formed over side walls and bottom surface of the connecting hole, and a second conductor layer formed over the second barrier metal layer to embed the connecting hole; wherein, at a joint between the connecting portion and wiring portion, at least one of the second barrier metal layer and capping barrier metal film on the bottom surface of the connecting hole is removed.

摘要翻译： 半导体器件具有具有布线沟槽的第一层间绝缘膜; 布线部分，其具有形成在所述布线沟槽的侧壁和底表面上的第一阻挡金属层，形成在所述第一阻挡金属层上以嵌入所述布线沟槽的第一导体层和形成在所述第一导体层上的封盖阻挡金属膜 ; 第二层间绝缘膜，形成在所述第一层间绝缘膜上并具有连接孔; 以及连接部，其具有形成在所述连接孔的侧壁和下表面上的第二阻挡金属层，以及形成在所述第二阻挡金属层上以嵌入所述连接孔的第二导体层; 其中，在所述连接部分和所述布线部分之间的连接处，所述连接孔底面上的所述第二阻挡金属层和覆盖阻挡金属膜中的至少一个被去除。

公开(公告)号：US06818546B2

公开(公告)日：2004-11-16

申请号：US09850162

申请日：2001-05-08

申请人： Tatsuyuki Saito ,  Naohumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

发明人： Tatsuyuki Saito ,  Naohumi Ohashi ,  Toshinori Imai ,  Junji Noguchi ,  Tsuyoshi Tamaru

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28562 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L21/76889 ,  H01L23/53295 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05027 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13

摘要： A barrier layer and a copper film are successively formed on a silicon oxide film including a groove for wiring in the silicon oxide film and a silicon nitride film, both formed on a semiconductor substrate. Thereafter, the barrier layer and the copper film are removed from outside of the groove for wiring, thereby forming a wiring. Tungsten is selectively or preferentially grown on the wiring to selectively form a tungsten film on the wiring. After the formation of the copper film, a treatment with hydrogen may be performed. After the formation of the wiring, the semiconductor substrate may be cleaned with a cleaning solution capable of removing a foreign matter or a contaminant metal. After the formation of the wiring, a treatment with hydrogen is carried out.

摘要翻译： 在半导体衬底上形成的氧化硅膜上形成有用于配线的沟槽的氧化硅膜和氮化硅膜，依次形成阻挡层和铜膜。 此后，从用于布线的槽的外侧除去阻挡层和铜膜，从而形成布线。 钨选择性地或优先地生长在布线上以在布线上选择性地形成钨膜。 铜膜形成后，可以进行氢处理。 在形成布线之后，可以用能够除去异物或污染金属的清洁溶液来清洁半导体衬底。 形成布线后，进行氢的处理。

公开(公告)号：US06326299B1

公开(公告)日：2001-12-04

申请号：US09361989

申请日：1999-07-28

申请人： Yoshio Homma ,  Seiichi Kondo ,  Noriyuki Sakuma ,  Naofumi Ohashi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada

发明人： Yoshio Homma ,  Seiichi Kondo ,  Noriyuki Sakuma ,  Naofumi Ohashi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada

IPC分类号： H01L214763

CPC分类号： H01L21/3212 ,  C09G1/02 ,  H01L21/7684

摘要： In order to suppress an increase of depressions, etc. to occur on a copper based alloy layer during polishing when a copper based alloy inlaid wiring is formed with the damascene method in grooves formed in an insulating film, the polishing rate for the lower metallic layer is set not less than five times faster than the etching rate for the same and the polishing rate for the insulating film is set lower than the polishing rate for the lower metallic layer when the upper metallic layer 13 to become a wiring and the lower metallic layer 12 to become a barrier are polished respectively. Thus, the object damascene wiring can be formed with less erosion on each of insulating layers and dishing on each of metallic layers respectively.

摘要翻译： 为了抑制在绝缘膜中形成的槽中以镶嵌法形成铜基合金镶嵌布线时在抛光期间在铜基合金层上发生的凹陷等的增加，下金属层的研磨速度 设定为比其蚀刻速度快五倍以上，并且当上金属层13成为布线时，绝缘膜的抛光速率被设定为低于下金属层的抛光速率，下金属层 12成为屏障分别抛光。 因此，对象镶嵌布线可以分别形成在绝缘层和每个金属层上的凹陷上较少的侵蚀。

公开(公告)号：US08129275B2

公开(公告)日：2012-03-06

申请号：US12700784

申请日：2010-02-05

申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

IPC分类号： H01L21/44

CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

摘要翻译： 为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层 含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

公开(公告)号：US20100320568A1

公开(公告)日：2010-12-23

申请号：US12873668

申请日：2010-09-01

申请人： Tsuyoshi FUJIWARA ,  Toshinori IMAI ,  Takeshi SAIKAWA ,  Yoshihiro KAWASAKI ,  Mitsuhiro TOYA ,  Shunji MORI ,  Yoshiyuki OKABE

发明人： Tsuyoshi FUJIWARA ,  Toshinori IMAI ,  Takeshi SAIKAWA ,  Yoshihiro KAWASAKI ,  Mitsuhiro TOYA ,  Shunji MORI ,  Yoshiyuki OKABE

IPC分类号： H01L29/92

CPC分类号： H01L28/91 ,  H01L27/10852 ,  H01L28/87

摘要： Provided is a technology capable of reducing parasitic capacitance of a capacitor while reducing the space occupied by the capacitor. A stacked structure is obtained by forming, over a capacitor composed of a lower electrode, a capacitor insulating film and an intermediate electrode, another capacitor composed of the intermediate electrode, another capacitor insulating film and an upper electrode. Since the intermediate electrode has a step difference, each of the distance between the intermediate electrode and lower electrode and the distance between the intermediate electrode and upper electrode in a region other than the capacitor formation region becomes greater than that in the capacitor formation region. For example, the lower electrode is brought into direct contact with the capacitor insulating film in the capacitor formation region, while the lower electrode is not brought into direct contact with the capacitor insulating film in the region other than the capacitor formation region.

公开(公告)号：US20100136786A1

公开(公告)日：2010-06-03

申请号：US12700784

申请日：2010-02-05

申请人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

发明人： Naofumi Ohashi ,  Junji Noguchi ,  Toshinori Imai ,  Hizuru Yamaguchi ,  Nobuo Owada ,  Kenji Hinode ,  Yoshio Homma ,  Seiichi Kondo

IPC分类号： H01L21/768

CPC分类号： H01L21/0209 ,  G09G5/399 ,  H01L21/02074 ,  H01L21/3212 ,  H01L21/76838 ,  H01L21/7684 ,  Y10S438/906

摘要： In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

摘要翻译： 为了提供通过化学机械抛光（CMP）方法形成的金属配线的防腐蚀技术，根据本发明的半导体集成电路器件的制造方法包括以下步骤：形成Cu（或Cu合金）的金属层 含有Cu作为主要成分），然后通过化学机械抛光（CMP）方法平坦化金属层以形成金属布线; 防止晶片的平面化主面在金属布线的表面上形成疏水性保护膜; 将晶圆的防腐主面浸入或保持湿润状态，使其不会变干; 并将晶片的主要表面保持在潮湿状态。

公开(公告)号：US20080203531A1

公开(公告)日：2008-08-28

申请号：US12024140

申请日：2008-02-01

申请人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

发明人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Hiroshi Ashihara ,  Akira Ootaguro ,  Yoshihiro Kawasaki

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L23/5223 ,  H01L28/75 ,  H01L2924/0002 ,  H01L2924/00

摘要： In this invention, the film thicknesses of an upper barrier film of a lower electrode of a capacitive element and an upper barrier film of a metallic interconnect layer formed in the same layer as this is made thicker than the film thicknesses of upper barrier films of other metallic interconnect layers. Moreover, in this invention, the film thickness of the upper barrier film of the lower electrode of the capacitive element is controlled to be 110 nm or more, more preferably, 160 nm or more. A decrease in the dielectric voltage of the capacitive dielectric film due to cracks in the upper barrier film does not occur and the deposition temperature of the capacitive dielectric film can be made higher, so that a semiconductor device having a MIM capacitor with high performance and high capacitance can be achieved, where the dielectric voltage of the capacitive dielectric film is improved.

摘要翻译： 在本发明中，电容元件的下电极的上阻挡膜和与其形成的相同层中的金属互连层的上阻挡膜的膜厚比其他的上阻挡膜的膜厚更厚 金属互连层。 此外，在本发明中，电容元件的下电极的上阻挡膜的膜厚控制在110nm以上，更优选为160nm以上。 不会发生由于上阻挡膜中的裂纹引起的电容电介质膜的电介质电压的降低，并且可以使电容电介质膜的沉积温度更高，使得具有高性能和高的MIM电容器的半导体器件 可以实现电容，其中电容电介质膜的介电电压得到改善。

公开(公告)号：US06696357B2

公开(公告)日：2004-02-24

申请号：US10195716

申请日：2002-07-16

申请人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Tomohiro Shiraishi ,  Hiroshi Ashihara ,  Masaaki Yoshida

发明人： Toshinori Imai ,  Tsuyoshi Fujiwara ,  Tomohiro Shiraishi ,  Hiroshi Ashihara ,  Masaaki Yoshida

IPC分类号： H01L2160

CPC分类号： H01L24/05 ,  H01L21/76838 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48463 ,  H01L2224/48624 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

摘要： Peeling between a bonding pad and an insulating film which underlies the bonding pad is to be prevented. A laminate film constituted mainly by W which is higher in mechanical strength than a wiring layer using an Al alloy film as a main conductive layer and than a bonding pad, is formed within an aperture formed in silicon oxide films and is interposed between the wiring line and the bonding pad.

摘要翻译： 要防止接合焊盘与接合焊盘之下的绝缘膜之间的剥离。 主要由W构成的层叠膜形成在形成于氧化硅膜中的孔内，其机械强度高于使用Al合金膜作为主导电层的布线层和焊盘，并且插入在布线 和接合垫。