公开(公告)号：US20210134751A1

公开(公告)日：2021-05-06

申请号：US16673699

申请日：2019-11-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Ju LU ,  Chi-Han CHEN ,  Chang-Yu LIN ,  Jr-Wei LIN ,  Chih-Pin HUNG

IPC: H01L23/00

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

公开(公告)号：US20210134696A1

公开(公告)日：2021-05-06

申请号：US16676284

申请日：2019-11-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian HU ,  Meng-Kai SHIH ,  Chih-Pin HUNG

IPC: H01L23/367 ,  H01L23/13 ,  H01L23/427 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, an electronic component disposed on the substrate, a supporting structure disposed on the substrate and surrounding the electronic component, and a heat spreading structure disposed on the supporting structure. A length of the supporting structure and a length of the heat spreading structure are greater than a length of the substrate.

公开(公告)号：US20210074676A1

公开(公告)日：2021-03-11

申请号：US16563716

申请日：2019-09-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20200066612A1

公开(公告)日：2020-02-27

申请号：US16112248

申请日：2018-08-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Tang-Yuan CHEN ,  Jin-Feng YANG ,  Meng-Kai SHIH

IPC: H01L23/367 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device package includes a substrate, a first electronic component, a second electronic component, a heat dissipation lid and a thermal isolation. The substrate has a surface. The first electronic component and the second electronic component are over the surface of the substrate and arranged along a direction substantially parallel to the surface. The first electronic component and the second electronic component are separated by a space therebetween. The heat dissipation lid is over the first electronic component and the second electronic component. The heat dissipation lid defines one or more apertures at least over the space between the first electronic component and the second electronic component. The thermal isolation is in the one or more apertures of the heat dissipation lid.

公开(公告)号：US20170229393A1

公开(公告)日：2017-08-10

申请号：US15019783

申请日：2016-02-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi HSIEH ,  Chih-Pin HUNG

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/535

CPC classification number: H01L23/5227 ,  H01L23/49822

Abstract: A semiconductor device includes a substrate and at least one inductor on the substrate. The inductor includes top portions separated from one another, bottom portions separated from one another, and side portions separated from one other. Each side portion extends between one of the top portions and one of the bottom portions. A semiconductor device includes a substrate, a first patterned conductive layer on the substrate, a second patterned conductive layer, and at least one dielectric layer between the first patterned conductive layer and the second patterned conductive layer. The first patterned conductive layer defines bottom crossbars separated from each other, each bottom crossbar including a bend angle. The second patterned conductive layer defines top crossbars separated from each other, wherein each top crossbar is electrically connected to a bottom crossbar.

公开(公告)号：US20240113061A1

公开(公告)日：2024-04-04

申请号：US18530123

申请日：2023-12-05

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Mei-Ju LU ,  Chi-Han CHEN ,  Chang-Yu LIN ,  Jr-Wei LIN ,  Chih-Pin HUNG

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02377 ,  H01L2224/02381 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/1703 ,  H01L2224/17177 ,  H01L2224/73204 ,  H01L2224/81951

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

公开(公告)号：US20220068839A1

公开(公告)日：2022-03-03

申请号：US17003883

申请日：2020-08-26

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Hsien KE ,  Teck-Chong LEE ,  Chih-Pin HUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L21/56

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.

公开(公告)号：US20220056589A1

公开(公告)日：2022-02-24

申请号：US17000239

申请日：2020-08-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chun-Wei CHIANG ,  Shin-Luh TARNG ,  Chih-Pin HUNG ,  Shiu-Chih WANG ,  Yong-Da CHIU

IPC: C23C18/16 ,  H01L21/67 ,  H01L21/768

Abstract: An electroless semiconductor bonding structure, an electroless plating system and an electroless plating method of the same are provided. The electroless semiconductor bonding structure includes a first substrate and a second substrate. The first substrate includes a first metal bonding structure disposed adjacent to a first surface of the first substrate. The second substrate includes a second metal bonding structure disposed adjacent to a second surface of the second substrate. The first metal bonding structure connects to the second metal bonding structure at an interface by electroless bonding and the interface is substantially void free.

公开(公告)号：US20190206684A1

公开(公告)日：2019-07-04

申请号：US16297480

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard HUNT ,  William T. Chen ,  Chih-Pin HUNG ,  Chen-Chao WANG

IPC: H01L21/108 ,  H01L23/528 ,  H01L23/00 ,  H01L23/04 ,  H01L21/768 ,  H01L23/485 ,  H01L25/065 ,  H01L23/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/16 ,  H01L21/56 ,  H01L27/108

CPC classification number: H01L21/108 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76801 ,  H01L23/04 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/10829 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.

公开(公告)号：US20190206683A1

公开(公告)日：2019-07-04

申请号：US16297477

申请日：2019-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： John Richard HUNT ,  William T. Chen ,  Chih-Pin HUNG ,  Chen-Chao WANG

IPC: H01L21/108 ,  H01L23/528 ,  H01L23/00 ,  H01L23/04 ,  H01L21/768 ,  H01L23/485 ,  H01L25/065 ,  H01L23/48 ,  H01L21/683 ,  H01L23/538 ,  H01L23/16 ,  H01L21/56 ,  H01L27/108

CPC classification number: H01L21/108 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76801 ,  H01L23/04 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/48 ,  H01L23/485 ,  H01L23/5283 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/45 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L27/10829 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/81

Abstract: A semiconductor device package includes: (1) an electronic device including an active surface and a contact pad adjacent to the active surface; and (2) a redistribution stack including a dielectric layer disposed over the active surface and defining a first opening exposing at least a portion of the contact pad; and a redistribution layer (RDL) disposed over the dielectric layer and including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and the maximum width of the second portion of the first trace is no greater than 3 times of a width of the first portion of the first trace, wherein the second portion of the first trace is disposed between and spaced from opposing sidewalls of the dielectric layer defining the first opening.