ELECTRONIC PACKAGE STRUCTURE
    12.
    发明申请
    ELECTRONIC PACKAGE STRUCTURE 有权
    电子包装结构

    公开(公告)号:US20160260656A1

    公开(公告)日:2016-09-08

    申请号:US14984554

    申请日:2015-12-30

    IPC分类号: H01L23/495 H01L23/31

    摘要: An electronic package includes a lead frame structure having one or more structural features configured to improve board level reliability. In one embodiment, the structural feature comprises lead frame protrusions extending outward from the electronic package, which are configured to laterally engage solder structures used to attach the electronic package to a next level of assembly. In another embodiment, conductive bumps are attached to exposed portions of the lead frame in advance of next level assembly processes. In a further embodiment, the lead frame comprises laterally separated contact points for attaching an electron die and for attaching the electronic package to a next level of assembly.

    摘要翻译: 电子封装包括具有一个或多个结构特征的引线框架结构,其被配置为提高电路板级可靠性。 在一个实施例中,结构特征包括从电子封装向外延伸的引线框架突起,其构造成横向接合用于将电子封装附接到下一级组装的焊接结构。 在另一个实施例中,导电凸块在下一级组装过程之前被附接到引线框架的暴露部分。 在另一实施例中,引线框架包括横向分开的接触点,用于附接电子管芯并将电子封装件附接到下一级组装。

    Semiconductor package having routable encapsulated conductive substrate and method

    公开(公告)号:US10685897B2

    公开(公告)日:2020-06-16

    申请号:US16032295

    申请日:2018-07-11

    摘要: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

    SEMICONDUCTOR PACKAGE HAVING ROUTABLE ENCAPSULATED CONDUCTIVE SUBSTRATE AND METHOD

    公开(公告)号:US20180323129A1

    公开(公告)日:2018-11-08

    申请号:US16032295

    申请日:2018-07-11

    摘要: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer. In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed. A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads. A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer. The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure.

    METHOD OF FORMING A MOLDED SUBSTRATE ELECTRONIC PACKAGE AND STRUCTURE
    18.
    发明申请
    METHOD OF FORMING A MOLDED SUBSTRATE ELECTRONIC PACKAGE AND STRUCTURE 有权
    形成基底电子封装和结构的方法

    公开(公告)号:US20160276236A1

    公开(公告)日:2016-09-22

    申请号:US14984064

    申请日:2015-12-30

    摘要: In one embodiment, an electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns and a package body encapsulating the top surface of the insulating material and the electronic device, wherein the bottom land surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer.

    摘要翻译: 在一个实施例中,电子封装包括具有嵌入在绝缘层内的多个焊盘的衬底。 导电图案设置在相应的陆地顶表面的至少一部分上。 电子设备电连接到导电图案和封装绝缘材料和电子设备的顶表面的封装体,其中底部表面暴露于外部。 在另一个实施例中,绝缘层的顶部表面和顶部表面基本上是共面的,并且导电图案进一步与绝缘层顶表面的部分重叠。