公开(公告)号：US10164028B2

公开(公告)日：2018-12-25

申请号：US15547863

申请日：2016-04-06

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jun Cheng

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/417 ,  H01L21/34 ,  H01L29/45 ,  H01L29/786 ,  H01L27/12 ,  H01L29/40 ,  H01L29/66

Abstract: Provided are a thin film transistor, a manufacturing method therefor, an oxide back plate and a display apparatus. The thin film transistor comprises: an oxide active layer (4) and source and drain electrodes (6a, 6b) connected to the oxide active layer (4), wherein the source and drain electrodes (6a, 6b) comprise a main portion (M) and a connective portion (C), the main portion (M) being isolated from the active layer (4), and being electrically connected to the active layer (4) via the connective portion (C), and an electrical resistivity of the connective portion (C) is greater than that of the main portion (M). In the thin film transistor provided above, since the main portions of the source and drain electrodes are not in contact with the oxide active layer, a metal with a relatively high electrical conductivity can be used as the source and drain electrodes, without having a relatively great impact on the electrical performance of the oxide active layer.

公开(公告)号：US20180269352A1

公开(公告)日：2018-09-20

申请号：US15813803

申请日：2017-11-15

Applicant: BOE Technology Group Co., Ltd. ,  Beijing BOE Optoelectronics Technology Co., Ltd.

Inventor： Ting Tian ,  Ming Zhai ,  Shuqian Dou ,  Dayong Zhou ,  Jun Cheng ,  Xiaoliang Fu ,  Zhiqiang Fan ,  Taesung Kang

IPC: H01L33/00 ,  H01L33/06 ,  H01L33/12 ,  H01L33/28 ,  H01L33/30 ,  H01L33/32 ,  H01L33/34 ,  H01L33/62 ,  H01L25/075

CPC classification number: H01L33/0095 ,  H01L25/0753 ,  H01L27/153 ,  H01L27/156 ,  H01L33/06 ,  H01L33/12 ,  H01L33/28 ,  H01L33/30 ,  H01L33/32 ,  H01L33/34 ,  H01L33/62 ,  H01L2933/0066

Abstract: A manufacturing method of a light emitting diode device and a light emitting diode device are provided. The manufacturing method of the light emitting diode device includes: forming a light emitting lamination layer on a base substrate, the light emitting lamination layer including a first semiconductor layer, a first light emitting layer, a second semiconductor layer, a second light emitting layer and a third semiconductor layer sequentially formed on the base substrate; dividing the light emitting lamination layer to form a plurality of light emitting units spaced from each other, each light emitting unit including a first area and a second area spaced from each other; and removing the third semiconductor layer and the second light emitting layer in the first area to form a first sub light emitting unit, and the second area being used for forming a second sub light emitting unit.

公开(公告)号：US09847400B2

公开(公告)日：2017-12-19

申请号：US15313141

申请日：2016-03-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong Kong ,  Lung Pao Hsin ,  Jun Cheng

IPC: H01L29/10 ,  H01L29/45 ,  H01L21/768 ,  H01L21/311 ,  H01L29/786 ,  H01L21/4757 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/45 ,  H01L21/31144 ,  H01L21/47573 ,  H01L21/76802 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

Abstract: Embodiments of the present disclosure provide an array substrate and a manufacturing method thereof, and a display device. The array substrate includes a base substrate, a first electrode pattern, a second electrode pattern, and an active layer pattern disposed on the base substrate, a first electrode protection pattern coating the first electrode pattern, and a second electrode protection pattern coating the second electrode pattern. The active layer pattern is disposed between the first electrode pattern and the second electrode pattern. The first electrode protection pattern and the second electrode protection pattern are connected to two sides of the active layer pattern, respectively. The problem that, the active layer pattern cannot be connected to the first electrode pattern and the second electrode pattern due to the surface oxidation, when the first electrode pattern and the second electrode pattern adopt material with low resistance characteristic, is avoided, thus increasing the product yield.

公开(公告)号：US20170263735A1

公开(公告)日：2017-09-14

申请号：US15282270

申请日：2016-09-30

Applicant: BOE Technology Group Co., Ltd. ,  Hefei Xinsheng Optoelectronics Technology Co., Ltd

Inventor： Jun Cheng

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/441 ,  H01L21/02 ,  H01L29/786 ,  H01L21/426

CPC classification number: H01L29/66969 ,  H01L21/02274 ,  H01L21/426 ,  H01L21/441 ,  H01L29/7869

Abstract: A method of manufacturing a thin-film transistor (TFT) and a TFT are provided. The method of manufacturing the TFT includes, after depositing a semiconductor layer, oxidizing regions of the semiconductor layer corresponding to sputtering target gaps, so that oxygen vacancies at the regions corresponding to the sputtering target gaps can be decreased and oxygen vacancies on the semiconductor layer can be more uniform.

公开(公告)号：US09324735B2

公开(公告)日：2016-04-26

申请号：US14348434

申请日：2013-12-16

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jun Cheng ,  Haijing Chen ,  Chunsheng Jiang

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/45 ,  H01L29/423 ,  H01L21/467 ,  H01L29/66

CPC classification number: H01L27/1225 ,  H01L21/467 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/42384 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: The present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device. The array substrate includes a plurality of pixel units, each of which includes: a TFT area provided with a TFT including a gate, a gate insulation layer, an active area, a source and a drain; and a display area provided with a pixel electrode.

Abstract translation: 本发明提供一种阵列基板及其制造方法，显示面板和显示装置。 阵列基板包括多个像素单元，每个像素单元包括：TFT区域，其设置有包括栅极，栅极绝缘层，有源区域，源极和漏极的TFT; 以及设置有像素电极的显示区域。

公开(公告)号：US09312146B2

公开(公告)日：2016-04-12

申请号：US14354320

申请日：2013-10-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiangyong Kong ,  Jun Cheng ,  Dongfang Wang ,  Guangcai Yuan

IPC: H01L21/8234 ,  H01L21/445 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L27/12

CPC classification number: H01L21/445 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/41758 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78621 ,  H01L29/7869 ,  H01L2029/42388

Abstract: Embodiments of the invention provide a thin film transistor and a manufacturing method thereof and a display device. The thin film transistor includes a gate electrode, a gate insulation layer, an active layer, an ohmic contact layer, a source electrode and a drain electrode, and the source electrode and the drain electrode are connected to the active layer by the ohmic contact layer. The ohmic contact layer is provided at a lateral side of the active layer and contacts the lateral side of the active layer.

Abstract translation: 本发明的实施例提供一种薄膜晶体管及其制造方法和显示装置。 薄膜晶体管包括栅电极，栅极绝缘层，有源层，欧姆接触层，源电极和漏电极，源电极和漏电极通过欧姆接触层连接到有源层 。 欧姆接触层设置在有源层的侧面并接触有源层的侧面。

公开(公告)号：US12060226B2

公开(公告)日：2024-08-13

申请号：US17419695

申请日：2020-10-23

Applicant: Chongqing BOE Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Bing Li ,  Baibing Liu ,  Jun Cheng

IPC: B65G1/137 ,  G06Q10/047 ,  G06Q10/0631 ,  G06Q10/0633 ,  G06Q10/08 ,  G06Q50/04

CPC classification number: B65G1/1373 ,  G06Q10/047 ,  G06Q10/06314 ,  G06Q10/0633 ,  G06Q10/08 ,  G06Q50/04

Abstract: Provided is a method for delivering materials, including: acquiring a material delivery model of a target product, wherein the material delivery model includes a delivery route of the target product and a number of delivery times of each of a plurality of logistics transport devices travelling along the delivery route within unit time; generating, for each logistics transport device, delivery instructions within the unit time, based on the number of delivery times, wherein a number of the delivery instructions is equal to the number of delivery times of the corresponding logistics transport device; and sending the delivery instructions to the corresponding logistics transport devices.

公开(公告)号：US11980058B2

公开(公告)日：2024-05-07

申请号：US17486790

申请日：2021-09-27

Applicant: Hefei Xinsheng Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Haitao Wang ,  Qinghe Wang ,  Jun Wang ,  Tongshang Su ,  Jun Cheng

IPC: H10K59/121 ,  H10K59/12 ,  H10K59/126 ,  H10K59/131 ,  H10K71/00

CPC classification number: H10K59/1213 ,  H10K59/1216 ,  H10K59/126 ,  H10K59/131 ,  H10K71/00 ,  H10K59/1201

Abstract: A display substrate, a preparation method thereof, and a display apparatus are provide. The display substrate includes: a base substrate, an active layer disposed on the base substrate, a first gate insulating layer disposed on the active layer, a first conductive layer disposed on the first gate insulating layer, and a second conductive layer disposed on the first conductive layer and electrically connected with the first conductive layer; an orthographic projection of the first conductive layer on the base substrate does not overlap with an orthographic projection of the active layer on the base substrate; the second conductive layer includes gates; orthographic projections of the gates on the base substrate and the orthographic projection of the active layer on the base substrate have an overlap area; and the display substrate further includes: at least one insulating layer located between the first conductive layer and the gates.

公开(公告)号：US11930679B2

公开(公告)日：2024-03-12

申请号：US17264283

申请日：2020-05-12

Applicant: Hefei Xinsheng Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Jingang Fang ,  Luke Ding ,  Jun Liu ,  Bin Zhou ,  Jun Cheng

IPC: H10K59/35 ,  H01L27/12 ,  H10K50/86 ,  H10K59/12 ,  H10K59/121 ,  H10K59/123 ,  H10K59/124 ,  H10K71/00

CPC classification number: H10K59/353 ,  H10K50/865 ,  H10K59/1213 ,  H10K71/00 ,  H10K59/1201

Abstract: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.

公开(公告)号：US11592742B2

公开(公告)日：2023-02-28

申请号：US16320041

申请日：2018-05-22

Applicant: Hefei Xinsheng Optoelectronics Technology Co., Ltd. ,  BOE Technology Group Co., Ltd.

Inventor： Wei Li ,  Guangcai Yuan ,  Bin Zhou ,  Dongfang Wang ,  Jun Cheng ,  Yingbin Hu ,  Jingjing Xia ,  Tongshang Su

IPC: G03F7/021 ,  G03F7/038 ,  G03F7/039 ,  G03F7/027 ,  H01L21/027 ,  H01L21/283 ,  H01L21/3213 ,  H01L21/77

Abstract: A photoresist composition and manufacturing method thereof, a manufacturing method of a metal pattern, and a manufacturing method of an array substrate are provided. The photoresist composition includes a base material and an ion adsorbent, and the ion adsorbent is chelating resin.